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annotate src/cs/drivers/drv_core/abb/abb.h @ 698:4f458e31b6e1

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.../drv_core/abb/abb.[ch]: sync with Tourmaline The changes being synced are: 1) ABB semaphore protection overhaul; 2) New ABB_SLEEP_RESTRICTION definition in fc-target.h
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 09 Jun 2021 18:00:44 +0000
parents 07818fb33771
children
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1 /**********************************************************************************/
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2 /* TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION */
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3 /* */
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4 /* Property of Texas Instruments -- For Unrestricted Internal Use Only */
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5 /* Unauthorized reproduction and/or distribution is strictly prohibited. This */
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6 /* product is protected under copyright law and trade secret law as an */
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7 /* unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All */
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8 /* rights reserved. */
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9 /* */
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10 /* */
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11 /* Filename : abb.h */
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12 /* */
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13 /* Description : Analog BaseBand registers and bits definition. */
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14 /* Functions to drive the ABB device. */
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15 /* The Serial Port Interface is used to connect the TI */
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16 /* Analog BaseBand (ABB). */
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17 /* It is assumed that the ABB is connected as the SPI */
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18 /* device 0. */
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19 /* */
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20 /* Author : Pascal PUEL */
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21 /* */
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22 /* Version number : 1.3 */
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23 /* */
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24 /* Date and time : 08/22/03 */
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25 /* */
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26 /* Previous delta : Creation */
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27 /* */
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28 /**********************************************************************************/
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29
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30 #ifndef __ABB_H__
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31 #define __ABB_H__
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32
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33 #include "l1sw.cfg"
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34
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35 #if (OP_L1_STANDALONE == 0)
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36 #include "main/sys_types.h"
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37 #else
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38 #include "sys_types.h"
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39 #endif
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41
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42 #ifndef _WINDOWS
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43
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44
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45 #include "chipset.cfg"
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46
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49
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50 /*------------------------------------*/
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51 /* SYREN PG Definition */
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52 /*------------------------------------*/
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53
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54 #if (ANLG_FAM == 3) // SYREN
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55 #define S_PG_10 1
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56 #define S_PG_20 2
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57 #endif // (ANLG_FAM == 3)
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58
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60
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61 // DEFINITIONS FOR OMEGA/NAUSICA
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62 #if (ANLG_FAM == 1)
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63 // ABB PAGE
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64 #define PAGE0 0x0001
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65 #define PAGE1 0x0002
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66
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67 // ABB REGISTERS
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68 //=== PAGE 0 =======
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69 #define PAGEREG (1 << 1)
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70 #define APCDEL1 (2 << 1)
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71 #define BULDATA1_2 (3 << 1)
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72 #define TOGBR1 (4 << 1)
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73 #define TOGBR2 (5 << 1)
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74 #define VBDCTRL (6 << 1)
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75 #define AUXAFC1 (7 << 1)
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76 #define AUXAFC2 (8 << 1)
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77 #define AUXAPC (9 << 1)
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78 #define APCRAM (10 << 1)
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79 #define APCOFF (11 << 1)
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80 #define AUXDAC (12 << 1)
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81 #define MADCCTRL1 (13 << 1)
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82 #define MADCCTRL2 (14 << 1)
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83 #define VBATREG (15 << 1)
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84 #define VCHGREG (16 << 1)
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85 #define ICHGREG (17 << 1)
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86 #define VBKPREG (18 << 1)
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87 #define ADIN1REG (19 << 1)
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88 #define ADIN2REG (20 << 1)
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89 #define ADIN3REG (21 << 1)
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90 #define ADIN4XREG (22 << 1)
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91 #define ADIN5YREG (23 << 1)
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92 #define MADCSTAT (24 << 1)
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93 #define CHGREG (25 << 1)
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94 #define ITMASK (26 << 1)
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95 #define ITSTATREG (27 << 1)
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96 #define BCICTL1 (28 << 1)
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97 #define BCICTL2 (29 << 1)
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98 #define VRPCCTL2 (30 << 1)
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99 #define VRPCSTS (31 << 1)
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100
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101 //=== PAGE 1 =======
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102 #define PAGEREG (1 << 1)
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103 #define BULIOFF (2 << 1)
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104 #define BULQOFF (3 << 1)
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105 #define BULQDAC (4 << 1)
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106 #define BULIDAC (5 << 1)
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107 #define BBCTRL (6 << 1)
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108 #define VBUCTRL (7 << 1)
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109 #define VBCTRL (8 << 1)
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110 #define PWDNRG (9 << 1)
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111 #define TSC_TIMER (10 << 1)
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112 #define VRPCCTRL3 (11 << 1)
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113 #define APCOUT (12 << 1)
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114 #define VRPCBGT (18 << 1)
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115 #define TAPCTRL (19 << 1)
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116 #define TAPREG (20 << 1)
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117 #define AFCCTLADD (21 << 1)
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118 #define AFCOUT (22 << 1)
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119 #define VRPCCTRL1 (23 << 1)
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120 #define VRPCCTRL4 (24 << 1)
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121 #define APCDEL2 (26 << 1)
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122 #define ITSTATREG (27 << 1)
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123
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124 // Registers bit definitions
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125 // ABB device bits definition of register VBCTRL
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126 #define VDLAUX 0x001
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127 #define VDLEAR 0x002
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128 #define VBUZ 0x004
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129 #define VULSWITCH 0x008
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130 #define MICBIAS 0x010
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131 #define VALOOP 0x020
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132 #define VCLKMODE 0x040
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133 #define VSYNC 0x080
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134 #define VBDFAUXG 0x100
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135 #define VFBYP 0x200
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136
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137 // ABB device bits definition of register VBUCTRL
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138 #define DXEN 0x200
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139
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140 // ABB device bits definition of register VRPCSTS
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141 #define ONBSTS 0x01 // ON Button push flag
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142 #define ONRSTS 0x02 // Remote ON flag
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143 #define ITWSTS 0x04 // Wake-up IT flag
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144 #define CHGSTS 0x08 // Charger plug flag
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145 #define ONREFLT 0x10 // ON Button current state
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146 #define ORMRFLT 0x20 // Remote ON current state
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147 #define CHGPRES 0x40 // Charger plug current state
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148
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149 // ABB device bits definition of register ITSTATREG
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150 #define REMOT_IT_STS 0x02
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151 #define PUSHOFF_IT_STS 0x04
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152 #define CHARGER_IT_STS 0x08
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153 #define ADCEND_IT_STS 0x20
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154
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155 // On Nausica, if the PWR key is pressed, the bit is set, and cleared when released
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156 #define PWR_OFF_KEY_PRESSED (ONREFLT)
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157
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158 // ABB ADC Interrupts
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159 #define EOC_INTENA 0x03DF
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160 #define EOC_INTMASK 0x0020
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161
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162 // ABB ADC CHANNELS
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163 #define VBATCV 0x0001
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164 #define VCHGCV 0x0002
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165 #define ICHGCV 0x0004
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166 #define VBKPCV 0x0008
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167 #define ADIN1CV 0x0010
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168 #define ADIN2CV 0x0020
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169 #define ADIN3CV 0x0040
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170 #define vADIN4XCV 0x0080
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171 #define ADIN5XCV 0x0100
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172 #define ALL 0x01FF
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173 #define NONE 0x0000
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174
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175 // ABB MODULES
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176 #define MADC 0x8000
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177 #define AFC 0x2000
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178 #define ADAC 0x0800
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179 #define DCDC 0x0080
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180 #define ALLOFF 0x0000
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181
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182 // Definitions of OMEGA test modes for baseband windows
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183 #define TSPTEST1 0x001d
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184 #define TSPTEST2 0x001e
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185 #define AFCTEST 0x0010
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186 #define AFCNORM 0x0000
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187
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188
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189 // DEFINITIONS FOR IOTA
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190 #elif (ANLG_FAM == 2)
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191 // ABB PAGE
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192 #define PAGE0 0x0001
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193 #define PAGE1 0x0002
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194 #define PAGE2 0x0010
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195
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196 // ABB REGISTERS
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197 //=== PAGE 0 =======
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198 #define PAGEREG (1 << 1)
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199 #define APCDEL1 (2 << 1)
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200 #define BULDATA1_2 (3 << 1)
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201 #define TOGBR1 (4 << 1)
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202 #define TOGBR2 (5 << 1)
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203 #define VBDCTRL (6 << 1)
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204 #define AUXAFC1 (7 << 1)
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205 #define AUXAFC2 (8 << 1)
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206 #define AUXAPC (9 << 1)
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207 #define APCRAM (10 << 1)
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208 #define APCOFF (11 << 1)
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209 #define AUXDAC (12 << 1)
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210 #define MADCCTRL (13 << 1)
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211 #define VBATREG (15 << 1)
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212 #define VCHGREG (16 << 1)
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213 #define ICHGREG (17 << 1)
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214 #define VBKPREG (18 << 1)
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215 #define ADIN1REG (19 << 1)
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216 #define ADIN2REG (20 << 1)
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217 #define ADIN3REG (21 << 1)
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218 #define ADIN4REG (22 << 1)
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219 #define MADCSTAT (24 << 1)
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220 #define CHGREG (25 << 1)
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221 #define ITMASK (26 << 1)
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222 #define ITSTATREG (27 << 1)
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223 #define BCICTL1 (28 << 1)
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224 #define BCICTL2 (29 << 1)
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225 #define VRPCDEV (30 << 1)
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226 #define VRPCSTS (31 << 1)
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227
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228 //=== PAGE 1 =======
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229 #define PAGEREG (1 << 1)
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230 #define BULIOFF (2 << 1)
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231 #define BULQOFF (3 << 1)
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232 #define BULQDAC (4 << 1)
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233 #define BULIDAC (5 << 1)
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234 #define BBCTRL (6 << 1)
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235 #define VBUCTRL (7 << 1)
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236 #define VBCTRL1 (8 << 1)
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237 #define PWDNRG (9 << 1)
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238 #define VBPOP (10 << 1)
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239 #define VBCTRL2 (11 << 1)
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240 #define APCOUT (12 << 1)
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241 #define BCICONF (13 << 1)
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242 #define BULGCAL (14 << 1)
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243 #define TAPCTRL (19 << 1)
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244 #define TAPREG (20 << 1)
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245 #define AFCCTLADD (21 << 1)
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246 #define AFCOUT (22 << 1)
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247 #define VRPCSIM (23 << 1)
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248 #define AUXLED (24 << 1)
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249 #define APCDEL2 (26 << 1)
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250 #define ITSTATREG (27 << 1)
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251 #define VRPCMSKABB (29 << 1)
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252 #define VRPCCFG (30 << 1)
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253 #define VRPCMSK (31 << 1)
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254
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255 // Registers bit definitions
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256 // ABB device bits definition of register VBCTRL1
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257 #define VDLAUX 0x001
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258 #define VDLEAR 0x002
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259 #define VBUZ 0x004
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260 #define VULSWITCH 0x008
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261 #define MICBIAS 0x010
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262 #define VALOOP 0x020
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263 #define VCLKMODE 0x040
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264 #define VSYNC 0x080
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265 #define VBDFAUXG 0x100
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266 #define VFBYP 0x200
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267
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268 // ABB device bits definition of register VBCTRL2
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269 #define MICBIASEL 0x001
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270 #define VDLHSO 0x002
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271 #define MICNAUX 0x004
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272
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273 // ABB device bits definition of register VBUCTRL
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274 #define DXEN 0x200
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275
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276 // ABB device bits definition of register VBPOP
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277 #define HSODIS 0x001
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278 #define HSOCHG 0x002
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279 #define HSOAUTO 0x004
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280 #define EARDIS 0x008
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281 #define EARCHG 0x010
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282 #define EARAUTO 0x020
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283 #define AUXDIS 0x040
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284 #define AUXCHG 0x080
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285 #define AUXAUTO 0x100
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286
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287 // ABB device bits definition of register VRPCSTS
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288 #define ONBSTS 0x01 // ON Button push flag
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289 #define ONRSTS 0x02 // Remote ON flag
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290 #define ITWSTS 0x04 // Wake-up IT flag
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291 #define CHGSTS 0x08 // Charger plug flag
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292 #define ONREFLT 0x10 // ON Button current state
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293 #define ORMRFLT 0x20 // Remote ON current state
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294 #define CHGPRES 0x40 // Charger plug current state
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295
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296 // ABB device bits definition of register ITSTATREG
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297 #define REMOT_IT_STS 0x02
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298 #define PUSHOFF_IT_STS 0x04
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299 #define CHARGER_IT_STS 0x08
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300 #define ADCEND_IT_STS 0x20
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301
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302 // On Iota, the bit is set when the key is released and set when the key is pressed
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303 #define PWR_OFF_KEY_PRESSED (0)
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304
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305 // ABB ADC Interrupts
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306 #define EOC_INTENA 0x03DF
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307 #define EOC_INTMASK 0x0020
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308
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309 // ABB ADC CHANNELS
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310 #define VBATCV 0x0001
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311 #define VCHGCV 0x0002
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312 #define ICHGCV 0x0004
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313 #define VBKPCV 0x0008
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314 #define ADIN1CV 0x0010
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315 #define ADIN2CV 0x0020
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316 #define ADIN3CV 0x0040
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317 #define ADIN4CV 0x0080
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318 #define ALL 0x00FF
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319 #define NONE 0x0000
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320
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321 // ABB MODULES
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322 #define MADC 0x8000
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Mychaela Falconia <falcon@freecalypso.org>
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323 #define AFC 0x2000
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Mychaela Falconia <falcon@freecalypso.org>
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324 #define ADAC 0x0800
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325 #define DCDC 0x0080
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Mychaela Falconia <falcon@freecalypso.org>
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326 #define ALLOFF 0x0000
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327
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328 // Definitions of IOTA test modes
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329 #define TSPTEST1 0x001d
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330 #define TSPTEST2 0x001e
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331 #define AFCTEST 0x0010
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332 #define AFCNORM 0x0000
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333
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Mychaela Falconia <falcon@freecalypso.org>
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334 // Definition for IOTA test modes
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Mychaela Falconia <falcon@freecalypso.org>
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335 #define TSPEN 0x001a
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336 #define MADCTEST 0x0012
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337 #define TSPADC 0x0015
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338 #define TSPUP 0x0017
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339 #define TSPDN 0x0018
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340
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Mychaela Falconia <falcon@freecalypso.org>
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341 // Definition for IOTA Power Management
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Mychaela Falconia <falcon@freecalypso.org>
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342
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Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
343 //The duration of the SLPDLY counter must be greater than the process execution time:
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diff changeset
344 //DBB deep sleep routine included the IT check = DBB sleep routine and IT check
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345 //+ the seven 32Khz clock cycle interval needed to ABB in order to make effective the sleep abort write access in VRPCDEV ++ // register -> 7*T32Khz = = ABB IBIC propagation delay
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diff changeset
346 //+ 150us of short asynchronous wake-up time (approximately 4*T32Khz) = ULPD short sleep where Syren/IOTA aborts sleep and
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Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
347 // write DEVSLEEP = 0
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348
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Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
349
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
350
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
351
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Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
352 #define SLPDLY 0x001F // delay to set IOTA in sleep mode (unit: 20*T32Khz)
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Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
353 #define MASK_SLEEP_MODE 0x0000 // set the regulators in low consumption in sleep mode
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354
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Mychaela Falconia <falcon@freecalypso.org>
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355
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Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
356 // DEFINITIONS FOR SYREN
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Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
357 #elif (ANLG_FAM == 3)
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358
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Mychaela Falconia <falcon@freecalypso.org>
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359 // ABB PAGE
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
360 #define PAGE0 0x0001
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
361 #define PAGE1 0x0002
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
362 #define PAGE2 0x0010
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Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
363
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Mychaela Falconia <falcon@freecalypso.org>
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364 // ABB REGISTERS
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
365 //=== PAGE 0 =======
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Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
366 #define PAGEREG (1 << 1)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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367 #define APCDEL1 (2 << 1)
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Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
368 #define BULDATA1_2 (3 << 1)
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Mychaela Falconia <falcon@freecalypso.org>
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369 #define TOGBR1 (4 << 1)
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Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
370 #define TOGBR2 (5 << 1)
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Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
371 #define VBDCTRL (6 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
372 #define AUXAFC1 (7 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
373 #define AUXAFC2 (8 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
374 #define AUXAPC (9 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
375 #define APCRAM (10 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
376 #define APCOFF (11 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
377 #define AUXDAC (12 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
378 #define MADCCTRL (13 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
379 #define CHGIREG (14 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
380 #define VBATREG (15 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
381 #define VCHGREG (16 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
382 #define ICHGREG (17 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
383 #define VBKPREG (18 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
384 #define ADIN1REG (19 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
385 #define ADIN2REG (20 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
386 #define ADIN3REG (21 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
387 #define ADIN4REG (22 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
388 #define ADIN5REG (23 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
389 #define MADCSTAT (24 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
390 #define CHGVREG (25 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
391 #define ITMASK (26 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
392 #define ITSTATREG (27 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
393 #define BCICTL1 (28 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
394 #define BCICTL2 (29 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
395 #define VRPCDEV (30 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
396 #define VRPCSTS (31 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
397
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
398 //=== PAGE 1 =======
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
399 #define PAGEREG (1 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
400 #define BULIOFF (2 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
401 #define BULQOFF (3 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
402 #define BULQDAC (4 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
403 #define BULIDAC (5 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
404 #define BBCTRL (6 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
405 #define VBUCTRL (7 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
406 #define VBCTRL1 (8 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
407 #define PWDNRG (9 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
408 #define VBPOP (10 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
409 #define VBCTRL2 (11 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
410 #define APCOUT (12 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
411 #define BCICONF (13 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
412 #define BULGCAL (14 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
413 #define VAUDCTRL (15 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
414 #define VAUSCTRL (16 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
415 #define VAUOCTRL (17 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
416 #define VAUDPLL (18 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
417 #define TAPCTRL (19 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
418 #define TAPREG (20 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
419 #define AFCCTLADD (21 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
420 #define AFCOUT (22 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
421 #define VRPCSIMR (23 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
422 #define BCIWDOG (24 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
423 #define NONE8 (25 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
424 #define APCDEL2 (26 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
425 #define ITSTATREG (27 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
426
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
427 #if (ANLG_PG == S_PG_20) // SYREN PG2.0 ON EVACONSO
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
428 #define BBCFG (28 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
429 #else
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
430 #define NONE9 (28 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
431 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
432
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
433 #define VRPCMSKOFF (29 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
434 #define VRPCCFG (30 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
435 #define VRPCMSKSLP (31 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
436
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
437 //=== PAGE 2 =======
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
438
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
439 #if (ANLG_PG == S_PG_10) // SYREN PG1.0 ON ESAMPLE
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
440 #define BBCFG (5 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
441 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
442
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
443 #define VRPCABBTST (25 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
444 #define VRPCAUX (30 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
445 #define VRPCLDO (31 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
446
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
447 /* INSERT HERE OTHER DEVICES REGISTERS */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
448
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
449
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
450 // Registers bit definitions
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
451 /*** SYREN internal control bits ***/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
452
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
453 /** For reg. VBCTRL1 **/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
454 #define VULSWITCH 0x008
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
455 #define MICBIAS 0x010
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
456 #define VALOOP 0x020
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
457 #define VCLKMODE 0x040
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
458 #define VSYNC 0x080
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
459 #define VBDFAUXG 0x100
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
460 #define VFBYP 0x200
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
461
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
462 /** For reg. VBCTRL2 **/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
463 #define HSMICSEL 0x001
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
464 #define MICBIASEL 0x004
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
465 #define SPKG 0x008
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
466 #define HSOVMID 0x010
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
467 #define HSDIF 0x020
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
468
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
469 /** For reg. VBUCTRL **/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
470 #define DXEN 0x200
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
471
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
472 /** For reg. VBPOP **/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
473 #define HSODIS 0x001
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
474 #define HSOCHG 0x002
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
475 #define HSOAUTO 0x004
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
476 #define EARDIS 0x008
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
477 #define EARCHG 0x010
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
478 #define EARAUTO 0x020
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
479 #define AUXFDIS 0x040
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
480 #define AUXAUTO 0x080
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
481 #define AUXFBYP 0x200
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
482
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
483 // ABB device bits definition of register VRPCCFG
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
484 #define PWOND 0x20 // ON Button current state
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
485 #define CHGPRES 0x40
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
486
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
487 // ABB device bits definition of register ITSTATREG
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
488 #define REMOT_IT_STS 0x02
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
489 #define PUSHOFF_IT_STS 0x04
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
490 #define CHARGER_IT_STS 0x08
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
491 #define ADCEND_IT_STS 0x20
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
492
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
493 // ABB device bits definition of register VRPCSTS
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
494 #define ITWSTS 0x10 // Wake-up IT flag
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
495 #define PWONBSTS 0x20 // ON Button push flag
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
496 #define CHGSTS 0x40 // Charger plug flag
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
497 #define RPSTS 0x100 // Remote ON flag
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
498
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
499 // ABB ADC Interrupts
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
500 #define EOC_INTENA 0x03DF
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
501 #define EOC_INTMASK 0x0020
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
502
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
503 // ABB ADC CHANNELS (reg. MADCCTRL)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
504 #define VBATCV 0x0001
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
505 #define VCHGCV 0x0002
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
506 #define ICHGCV 0x0004
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
507 #define VBKPCV 0x0008
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
508 #define ADIN1CV 0x0010
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
509 #define ADIN2CV 0x0020
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
510 #define ADIN3CV 0x0040
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
511 #define ADIN4CV 0x0080
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
512 #define ADIN5CV 0x0100
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
513 #define ALL 0x01FF
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
514 #define NONE 0x0000
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
515
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
516 // ABB MODULES
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
517 #define MADC 0x8000
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
518 #define AFC 0x2000
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
519 #define ADAC 0x0800
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
520 #define DCDC 0x0080
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
521 #define ALLOFF 0x0000
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
522
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
523 // Definitions of SYREN test modes
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
524 #define TSPTEST1 0x001d
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
525 #define TSPTEST2 0x001e
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
526 #define AFCTEST 0x0010
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
527 #define AFCNORM 0x0000
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
528
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
529 #define TSPEN 0x001a
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
530 #define MADCTEST 0x0012
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
531 #define TSPADC 0x0015
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
532 #define TSPUP 0x0017
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
533 #define TSPDN 0x0018
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
534
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
535 // Definition for SYREN Power Management
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
536
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
537 //The duration of the SLPDLY counter must be greater than the process execution time:
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
538 //DBB deep sleep routine included the IT check = DBB sleep routine and IT check
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
539 //+ the seven 32Khz clock cycle interval needed to ABB in order to make effective the sleep abort write access in VRPCDEV ++ // register -> 7*T32Khz = = ABB IBIC propagation delay
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
540 //+ 150us of short asynchronous wake-up time (approximately 4*T32Khz) = ULPD short sleep where Syren/IOTA aborts sleep and
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
541 // write DEVSLEEP = 0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
542
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
543 #define SLPDLY 0x001F // delay to set SYREN in sleep mode (unit: 20*T32Khz)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
544 #define MASK_SLEEP_MODE 0x0000 // set the regulators in low consumption in sleep mode
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
545
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
546 #define LOCORE_SLEEP 0x01
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
547 #define NORMAL_SLEEP 0x00
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
548
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
549 #define MAIN_BG 0x01,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
550 #define SLEEP_BG 0x00
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
551
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
552 #endif // ANLG_FAM == 1,2,3
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
553
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
554
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
555 // Define the level of semaphore protection for all accesses to the ABB
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
556 // 0 for no protection
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
557 // 1 for protection low
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
558 // 2 for protection medium
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
559 // 3 for protection high
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
560 #if (OP_L1_STANDALONE == 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
561 #define ABB_SEMAPHORE_PROTECTION (0)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
562 #else
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 317
diff changeset
563 #define ABB_SEMAPHORE_PROTECTION (3)
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
564 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
565
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
566
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
567
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
568 // PROTOTYPES
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
569 #if (ABB_SEMAPHORE_PROTECTION)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
570 void ABB_Sem_Create(void);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
571 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
572 void ABB_Wait_IBIC_Access(void);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
573 void ABB_Write_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id, SYS_UWORD16 value);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
574 SYS_UWORD16 ABB_Read_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
575 void ABB_free_13M(void);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
576 void ABB_stop_13M(void);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
577 SYS_UWORD16 ABB_Read_Status(void);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
578 void ABB_Conf_ADC(SYS_UWORD16 Channels, SYS_UWORD16 ItVal);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
579 void ABB_Read_ADC(SYS_UWORD16 *Buff);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
580 void ABB_on(SYS_UWORD16 modules, SYS_UWORD8 bRecoveryFlag);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
581 SYS_UWORD32 ABB_sleep(SYS_UWORD8 sleep_performed, SYS_WORD16 afc);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
582 void ABB_wakeup(SYS_UWORD8 sleep_performed, SYS_WORD16 afc);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
583 void ABB_wa_VRPC(SYS_UWORD16 value);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
584 void ABB_Write_Uplink_Data(SYS_UWORD16 *TM_ul_data);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
585 #if (OP_L1_STANDALONE == 0)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
586 void ABB_Power_Off(void);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
587 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
588 #if (ANLG_FAM ==3)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
589 void Syren_Sleep_Config(SYS_UWORD16 sleep_type,SYS_UWORD16 bg_select, SYS_UWORD16 sleep_delay);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
590 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
591
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
592 #else // _WINDOWS
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
593 // DEFINITIONS FOR IOTA
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
594 // ABB PAGE
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
595 #define PAGE0 0x0001
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
596 #define PAGE1 0x0002
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
597 #define PAGE2 0x0010
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
598
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
599 // ABB REGISTERS
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
600 //=== PAGE 0 =======
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
601 #define PAGEREG (1 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
602 #define APCDEL1 (2 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
603 #define BULDATA1_2 (3 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
604 #define TOGBR1 (4 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
605 #define TOGBR2 (5 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
606 #define VBDCTRL (6 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
607 #define AUXAFC1 (7 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
608 #define AUXAFC2 (8 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
609 #define AUXAPC (9 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
610 #define APCRAM (10 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
611 #define APCOFF (11 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
612 #define AUXDAC (12 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
613 #define MADCCTRL (13 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
614 #define VBATREG (15 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
615 #define VCHGREG (16 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
616 #define ICHGREG (17 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
617 #define VBKPREG (18 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
618 #define ADIN1REG (19 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
619 #define ADIN2REG (20 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
620 #define ADIN3REG (21 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
621 #define ADIN4REG (22 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
622 #define MADCSTAT (24 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
623 #define CHGREG (25 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
624 #define ITMASK (26 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
625 #define ITSTATREG (27 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
626 #define BCICTL1 (28 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
627 #define BCICTL2 (29 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
628 #define VRPCDEV (30 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
629 #define VRPCSTS (31 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
630
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
631 //=== PAGE 1 =======
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
632 #define PAGEREG (1 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
633 #define BULIOFF (2 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
634 #define BULQOFF (3 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
635 #define BULQDAC (4 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
636 #define BULIDAC (5 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
637 #define BBCTRL (6 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
638 #define VBUCTRL (7 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
639 #define VBCTRL1 (8 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
640 #define PWDNRG (9 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
641 #define VBPOP (10 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
642 #define VBCTRL2 (11 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
643 #define APCOUT (12 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
644 #define BCICONF (13 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
645 #define BULGCAL (14 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
646 #define TAPCTRL (19 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
647 #define TAPREG (20 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
648 #define AFCCTLADD (21 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
649 #define AFCOUT (22 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
650 #define VRPCSIM (23 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
651 #define AUXLED (24 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
652 #define APCDEL2 (26 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
653 #define ITSTATREG (27 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
654 #define VRPCMSKABB (29 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
655 #define VRPCCFG (30 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
656 #define VRPCMSK (31 << 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
657
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
658 // ABB device bits definition of register VBUCTRL
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
659 #define DXEN 0x200
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
660
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
661 // ABB device bits definition of register VRPCSTS
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
662 #define ONBSTS 0x01 // ON Button push flag
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
663 #define ONRSTS 0x02 // Remote ON flag
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
664 #define ITWSTS 0x04 // Wake-up IT flag
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
665 #define CHGSTS 0x08 // Charger plug flag
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
666 #define ONREFLT 0x10 // ON Button current state
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
667 #define ORMRFLT 0x20 // Remote ON current state
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
668 #define CHGPRES 0x40 // Charger plug current state
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
669
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
670 // ABB device bits definition of register ITSTATREG
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
671 #define REMOT_IT_STS 0x02
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
672 #define PUSHOFF_IT_STS 0x04
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
673 #define CHARGER_IT_STS 0x08
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
674 #define ADCEND_IT_STS 0x20
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
675
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
676
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
677 // PROTOTYPES
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
678 void ABB_Write_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id, SYS_UWORD32 value);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
679 SYS_UWORD16 ABB_Read_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
680 SYS_UWORD16 ABB_Read_Status(void);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
681 void ABB_Conf_ADC(SYS_UWORD16 Channels, SYS_UWORD16 ItVal);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
682 void ABB_Read_ADC(SYS_UWORD16 *Buff);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
683
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
684 #endif // _WINDOWS
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
685
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
686 #endif // __ABB_H__