FreeCalypso > hg > fc-magnetite

annotate src/cs/drivers/drv_core/abb/abb.c @ 698:4f458e31b6e1

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
.../drv_core/abb/abb.[ch]: sync with Tourmaline The changes being synced are: 1) ABB semaphore protection overhaul; 2) New ABB_SLEEP_RESTRICTION definition in fc-target.h
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 09 Jun 2021 18:00:44 +0000
parents 337e6d3a4454
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1 /**********************************************************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
2 /* TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
3 /* */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
4 /* Property of Texas Instruments -- For Unrestricted Internal Use Only */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
5 /* Unauthorized reproduction and/or distribution is strictly prohibited. This */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
6 /* product is protected under copyright law and trade secret law as an */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
7 /* unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
8 /* rights reserved. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
9 /* */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
10 /* */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
11 /* Filename : abb.c */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
12 /* */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
13 /* Description : Functions to drive the ABB device. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
14 /* The Serial Port Interface is used to connect the TI */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
15 /* Analog BaseBand (ABB). */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
16 /* It is assumed that the ABB is connected as the SPI */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
17 /* device 0. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
18 /* */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
19 /* Author : Pascal PUEL */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
20 /* */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
21 /* Version number : 1.3 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
22 /* */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
23 /* Date and time : 08/22/03 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
24 /* */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
25 /* Previous delta : Creation */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
26 /* */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
27 /**********************************************************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
28
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
29 #include "l1sw.cfg"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
30
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
31 #include "chipset.cfg"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
32 #include "board.cfg"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
33 #include "rf.cfg"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
34 #include "swconfig.cfg"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
35 #include "sys.cfg"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
36 #include "abb.h"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
37 #include "l1_macro.h"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
38 #include "l1_confg.h"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
39 #include "clkm/clkm.h" // for wait_ARM_cycles function
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
40 #include "abb_inline.h"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
41 #include "ulpd/ulpd.h" // for FRAME_STOP definition
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
42 #include "nucleus.h" // for NUCLEUS functions and types
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
43 #include "l1_types.h"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
44
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
45 #if (OP_L1_STANDALONE == 0)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
46 #include "main/sys_types.h"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
47 #include "rv/general.h"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
48 #include "buzzer/buzzer.h" // for BZ_KeyBeep_OFF function
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
49 #else
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
50 #include "sys_types.h"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
51 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
52
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
53 #if (VCXO_ALGO == 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
54 #include "l1_ctl.h"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
55 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
56
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
57 #if (RF_FAM == 35)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
58 #include "l1_rf35.h"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
59 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
60
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
61 #if (RF_FAM == 12)
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
62 #include "tpudrv12.h"
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
63 #include "l1_rf12.h"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
64 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
65
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
66 #if (RF_FAM == 10)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
67 #include "l1_rf10.h"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
68 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
69
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
70 #if (RF_FAM == 8)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
71 #include "l1_rf8.h"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
72 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
73
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
74 #if (RF_FAM == 2)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
75 #include "l1_rf2.h"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
76 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
77
327
d7b25dca1266 .../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
78 /*
d7b25dca1266 .../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
79 * The following conditional compilation control is a FreeCalypso addition.
d7b25dca1266 .../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
80 * TI's original code always configured the BCICONF register with
d7b25dca1266 .../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
81 * MESBB and BBCHGEN bits set, enabling both charging and the measurement
d7b25dca1266 .../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
82 * resistive divider for the backup battery. However, on our primary
d7b25dca1266 .../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
83 * hw targets (Openmoko GTA02 and our own FCDEV3B) Iota's VBACKUP pin
d7b25dca1266 .../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
84 * is unconnected, whereas on Mot C139 and Pirelli DP-L10 "alien" hw
d7b25dca1266 .../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
85 * the VBACKUP situation is unclear. But at least on our known hw
d7b25dca1266 .../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
86 * with VBACKUP unconnected, it is better to leave backup battery charging
d7b25dca1266 .../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
87 * and measurement OFF - TI's original config seems to be a drain on
d7b25dca1266 .../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
88 * the main battery. Therefore, we are going to leave MESBB and BBCHGEN
d7b25dca1266 .../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
89 * off until and unless we have a hw target where backup battery charging
d7b25dca1266 .../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
90 * and measurement are appropriate.
d7b25dca1266 .../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
91 */
d7b25dca1266 .../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
92
d7b25dca1266 .../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
93 #define ENABLE_BACKUP_BATTERY 0
d7b25dca1266 .../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
94
648
337e6d3a4454 abb.c: disable superdeep sleep on Luna
Mychaela Falconia <falcon@freecalypso.org>
parents: 327
diff changeset
95 /*
337e6d3a4454 abb.c: disable superdeep sleep on Luna
Mychaela Falconia <falcon@freecalypso.org>
parents: 327
diff changeset
96 * The following ABB_sleep_allowed global variable is yet another FreeCalypso
337e6d3a4454 abb.c: disable superdeep sleep on Luna
Mychaela Falconia <falcon@freecalypso.org>
parents: 327
diff changeset
97 * addition. Here is the issue: some handset boards have the controller/driver
337e6d3a4454 abb.c: disable superdeep sleep on Luna
Mychaela Falconia <falcon@freecalypso.org>
parents: 327
diff changeset
98 * chip in the LCD powered from Iota VRIO, which is generally a very sensible
337e6d3a4454 abb.c: disable superdeep sleep on Luna
Mychaela Falconia <falcon@freecalypso.org>
parents: 327
diff changeset
99 * arrangement. As one reference example, our 176x220 pixel TFT LCDs which
337e6d3a4454 abb.c: disable superdeep sleep on Luna
Mychaela Falconia <falcon@freecalypso.org>
parents: 327
diff changeset
100 * we are considering for our own FC handset draw about 3 mA from their Vci
337e6d3a4454 abb.c: disable superdeep sleep on Luna
Mychaela Falconia <falcon@freecalypso.org>
parents: 327
diff changeset
101 * supply which we connect to VRIO - perfectly fine when the regulators are
337e6d3a4454 abb.c: disable superdeep sleep on Luna
Mychaela Falconia <falcon@freecalypso.org>
parents: 327
diff changeset
102 * in their normal Active mode. But what about sleep mode? Sleep mode VRIO
337e6d3a4454 abb.c: disable superdeep sleep on Luna
Mychaela Falconia <falcon@freecalypso.org>
parents: 327
diff changeset
103 * current limit is only 1 mA, thus the combination of the LCD being on and
337e6d3a4454 abb.c: disable superdeep sleep on Luna
Mychaela Falconia <falcon@freecalypso.org>
parents: 327
diff changeset
104 * drawing 3 mA with the ABB in sleep mode is invalid. TI's original code
337e6d3a4454 abb.c: disable superdeep sleep on Luna
Mychaela Falconia <falcon@freecalypso.org>
parents: 327
diff changeset
105 * already had a check for VRPCSTS: PWON and RPWON need to be released and
337e6d3a4454 abb.c: disable superdeep sleep on Luna
Mychaela Falconia <falcon@freecalypso.org>
parents: 327
diff changeset
106 * the charger needs to be unplugged in order to enter ABB superdeep sleep.
337e6d3a4454 abb.c: disable superdeep sleep on Luna
Mychaela Falconia <falcon@freecalypso.org>
parents: 327
diff changeset
107 * We are extending this check with one more condition: ABB_sleep_allowed
337e6d3a4454 abb.c: disable superdeep sleep on Luna
Mychaela Falconia <falcon@freecalypso.org>
parents: 327
diff changeset
108 * needs to be nonzero; the intent is that this variable will be set by the
337e6d3a4454 abb.c: disable superdeep sleep on Luna
Mychaela Falconia <falcon@freecalypso.org>
parents: 327
diff changeset
109 * code responsible for putting the LCD into its own powerdown mode.
337e6d3a4454 abb.c: disable superdeep sleep on Luna
Mychaela Falconia <falcon@freecalypso.org>
parents: 327
diff changeset
110 * This logic is included only for affected targets with LCDs.
337e6d3a4454 abb.c: disable superdeep sleep on Luna
Mychaela Falconia <falcon@freecalypso.org>
parents: 327
diff changeset
111 */
337e6d3a4454 abb.c: disable superdeep sleep on Luna
Mychaela Falconia <falcon@freecalypso.org>
parents: 327
diff changeset
112
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
113 #ifdef ABB_SLEEP_RESTRICTION
648
337e6d3a4454 abb.c: disable superdeep sleep on Luna
Mychaela Falconia <falcon@freecalypso.org>
parents: 327
diff changeset
114 int ABB_sleep_allowed = 0;
337e6d3a4454 abb.c: disable superdeep sleep on Luna
Mychaela Falconia <falcon@freecalypso.org>
parents: 327
diff changeset
115 #endif
337e6d3a4454 abb.c: disable superdeep sleep on Luna
Mychaela Falconia <falcon@freecalypso.org>
parents: 327
diff changeset
116
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
117 #if (ABB_SEMAPHORE_PROTECTION)
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
118
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
119 static NU_SEMAPHORE abb_sem;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
120
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
121 /*-----------------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
122 /* ABB_Sem_Create() */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
123 /* */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
124 /* This function creates the Nucleus semaphore to protect ABB accesses */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
125 /* against preemption. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
126 /* No check on the result. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
127 /* */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
128 /*-----------------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
129 void ABB_Sem_Create(void)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
130 {
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
131 // create a semaphore with an initial count of 1 and with FIFO type suspension.
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
132 NU_Create_Semaphore(&abb_sem, "ABB_SEM", 1, NU_FIFO);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
133 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
134
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
135 #endif // ABB_SEMAPHORE_PROTECTION
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
136
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
137 /*-----------------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
138 /* ABB_Wait_IBIC_Access() */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
139 /* */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
140 /* This function waits for the first IBIC access. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
141 /* */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
142 /*-----------------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
143 void ABB_Wait_IBIC_Access(void)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
144 {
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
145 #if (ANLG_FAM == 1)
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
146 // Wait 6 OSCAS cycles (100 KHz) for first IBIC access
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
147 // (i.e wait 60us + 10% security marge = 66us)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
148 wait_ARM_cycles(convert_nanosec_to_cycles(66000));
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
149 #elif ((ANLG_FAM == 2) || (ANLG_FAM == 3))
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
150 // Wait 6 x 32 KHz clock cycles for first IBIC access
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
151 // (i.e wait 187us + 10% security marge = 210us)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
152 wait_ARM_cycles(convert_nanosec_to_cycles(210000));
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
153 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
154 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
155
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
156
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
157 /*-----------------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
158 /* ABB_Write_Register_on_page() */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
159 /* */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
160 /* This function manages all the spi serial transfer to write to an */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
161 /* ABB register on a specified page. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
162 /* */
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
163 /*-----------------------------------------------------------------------*/
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
164 void ABB_Write_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id, SYS_UWORD16 value)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
165 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
166 volatile SYS_UWORD16 status;
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
167 STATUS sem_status;
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
168
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
169 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3))
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
170
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
171 // check if the semaphore has been correctly created and try to obtain it.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
172 // if the semaphore cannot be obtained, the task is suspended and then resumed
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
173 // as soon as the semaphore is released.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
174
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
175 sem_status = NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND);
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
176
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
177 #endif // ABB_SEMAPHORE_PROTECTION
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
178
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
179 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags.
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
180 SPI_Ready_for_WR
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
181 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
182
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
183 // set the ABB page for register access
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
184 ABB_SetPage(page);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
185
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
186 // Write value in reg_id
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
187 ABB_WriteRegister(reg_id, value);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
188
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
189 // set the ABB page for register access at page 0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
190 ABB_SetPage(PAGE0);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
191
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
192 // Stop the SPI clock
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
193 #ifdef SPI_CLK_LOW_POWER
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
194 SPI_CLK_DISABLE
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
195 #endif
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
196
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
197 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3))
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
198 // release the semaphore only if it has correctly been created.
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
199 if(sem_status == NU_SUCCESS)
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
200 {
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
201 NU_Release_Semaphore(&abb_sem);
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
202 }
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
203 #endif // ABB_SEMAPHORE_PROTECTION
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
204 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
205
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
206
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
207 /*-----------------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
208 /* ABB_Read_Register_on_page() */
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
209 /* */
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
210 /* This function manages all the spi serial transfer to read one */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
211 /* ABB register on a specified page. */
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
212 /* */
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
213 /* Returns the real data value of the register. */
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
214 /* */
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
215 /*-----------------------------------------------------------------------*/
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
216 SYS_UWORD16 ABB_Read_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
217 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
218 volatile SYS_UWORD16 status;
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
219 STATUS sem_status;
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
220 SYS_UWORD16 reg_val;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
221
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
222 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3))
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
223
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
224 // check if the semaphore has been correctly created and try to obtain it.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
225 // if the semaphore cannot be obtained, the task is suspended and then resumed
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
226 // as soon as the semaphore is released.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
227
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
228 sem_status = NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND);
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
229
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
230 #endif // ABB_SEMAPHORE_PROTECTION
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
231
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
232 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags.
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
233 SPI_Ready_for_RDWR
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
234 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
235
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
236 /* set the ABB page for register access */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
237 ABB_SetPage(page);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
238
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
239 /* Read selected ABB register */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
240 reg_val = ABB_ReadRegister(reg_id);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
241
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
242 /* set the ABB page for register access at page 0 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
243 ABB_SetPage(PAGE0);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
244
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
245 // Stop the SPI clock
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
246 #ifdef SPI_CLK_LOW_POWER
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
247 SPI_CLK_DISABLE
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
248 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
249
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
250 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3))
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
251 // release the semaphore only if it has correctly been created.
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
252 if(sem_status == NU_SUCCESS)
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
253 {
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
254 NU_Release_Semaphore(&abb_sem);
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
255 }
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
256 #endif // ABB_SEMAPHORE_PROTECTION
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
257
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
258 return (reg_val); // Return result
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
259 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
260
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
261 /*------------------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
262 /* ABB_free_13M() */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
263 /* */
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
264 /* This function sets the 13M clock working in ABB. A wait loop */
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
265 /* is required to allow first slow access to ABB clock register. */
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
266 /* */
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
267 /* WARNING !! : this function must not be protected by semaphore !! */
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
268 /* */
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
269 /*------------------------------------------------------------------------*/
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
270 void ABB_free_13M(void)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
271 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
272 volatile SYS_UWORD16 status;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
273
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
274 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags.
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
275 SPI_Ready_for_WR
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
276 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
277
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
278 ABB_SetPage(PAGE0);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
279
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
280 // This transmission frees the CLK13 in ABB.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
281 ABB_WriteRegister(TOGBR2, 0x08);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
282
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
283 // Wait for first IBIC access
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
284 ABB_Wait_IBIC_Access();
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
285
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
286 // SW Workaround : This transmission has to be done twice.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
287 ABB_WriteRegister(TOGBR2, 0x08);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
288
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
289 // Wait for first IBIC access
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
290 ABB_Wait_IBIC_Access();
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
291
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
292 // Stop the SPI clock
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
293 #ifdef SPI_CLK_LOW_POWER
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
294 SPI_CLK_DISABLE
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
295 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
296 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
297
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
298
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
299 /*------------------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
300 /* ABB_stop_13M() */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
301 /* */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
302 /* This function stops the 13M clock in ABB. */
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
303 /* */
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
304 /*------------------------------------------------------------------------*/
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
305 void ABB_stop_13M(void)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
306 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
307 volatile SYS_UWORD16 status;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
308
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
309 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags.
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
310 SPI_Ready_for_WR
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
311 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
312
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
313 ABB_SetPage(PAGE0);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
314
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
315 // Set ACTIVMCLK = 0.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
316 ABB_WriteRegister(TOGBR2, 0x04);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
317
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
318 // Wait for first IBIC access
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
319 ABB_Wait_IBIC_Access();
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
320
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
321 // Stop the SPI clock
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
322 #ifdef SPI_CLK_LOW_POWER
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
323 SPI_CLK_DISABLE
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
324 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
325 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
326
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
327
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
328 /*------------------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
329 /* ABB_Read_Status() */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
330 /* */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
331 /* This function reads and returns the value of VRPCSTS ABB register. */
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
332 /* */
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
333 /*------------------------------------------------------------------------*/
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
334 SYS_UWORD16 ABB_Read_Status(void)
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
335 {
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
336 volatile SYS_UWORD16 status;
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
337 STATUS sem_status;
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
338 SYS_UWORD16 reg_val;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
339
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
340 #if ((ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3))
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
341
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
342 // check if the semaphore has been correctly created and try to obtain it.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
343 // if the semaphore cannot be obtained, the task is suspended and then resumed
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
344 // as soon as the semaphore is released.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
345
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
346 sem_status = NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND);
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
347
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
348 #endif // ABB_SEMAPHORE_PROTECTION
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
349
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
350 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags.
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
351 SPI_Ready_for_WR
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
352 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
353
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
354 ABB_SetPage(PAGE0);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
355
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
356 #if (ANLG_FAM == 1) || (ANLG_FAM == 2)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
357 ABB_SetPage(PAGE0);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
358 reg_val = ABB_ReadRegister(VRPCSTS);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
359 #elif (ANLG_FAM == 3)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
360 ABB_SetPage(PAGE1);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
361 reg_val = ABB_ReadRegister(VRPCCFG);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
362 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
363
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
364 // Stop the SPI clock
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
365 #ifdef SPI_CLK_LOW_POWER
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
366 SPI_CLK_DISABLE
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
367 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
368
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
369 #if ((ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3))
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
370 // release the semaphore only if it has correctly been created.
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
371 if(sem_status == NU_SUCCESS)
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
372 {
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
373 NU_Release_Semaphore(&abb_sem);
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
374 }
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
375 #endif // ABB_SEMAPHORE_PROTECTION
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
376
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
377 return (reg_val);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
378 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
379
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
380 /*------------------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
381 /* ABB_on() */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
382 /* */
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
383 /* This function configures ABB registers to work in ON condition */
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
384 /* */
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
385 /*------------------------------------------------------------------------*/
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
386 void ABB_on(SYS_UWORD16 modules, SYS_UWORD8 bRecoveryFlag)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
387 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
388 volatile SYS_UWORD16 status;
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
389 STATUS sem_status;
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
390 #if ((ANLG_FAM == 2) || (ANLG_FAM == 3))
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
391 SYS_UWORD32 reg;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
392 #endif
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
393
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
394 #if (ABB_SEMAPHORE_PROTECTION == 3)
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
395
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
396 // check if the semaphore has been correctly created and try to obtain it.
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
397 // if the semaphore cannot be obtained, the task is suspended and then resumed
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
398 // as soon as the semaphore is released.
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
399
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
400 sem_status = NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND);
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
401
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
402 #endif // ABB_SEMAPHORE_PROTECTION
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
403
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
404 // a possible cause of the recovery is that ABB is on Oscas => switch from Oscas to CLK13
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
405 if (bRecoveryFlag)
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
406 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
407 // RESTITUTE 13MHZ CLOCK TO ABB
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
408 //---------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
409 ABB_free_13M();
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
410
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
411 // RESTITUTE 13MHZ CLOCK TO ABB AGAIN (C.F. BUG1719)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
412 //---------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
413 ABB_free_13M();
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
414 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
415
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
416 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags.
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
417 SPI_Ready_for_RDWR
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
418 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
419
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
420 ABB_SetPage(PAGE0);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
421
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
422 // This transmission disables MADC,AFC,VDL,VUL modules.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
423 ABB_WriteRegister(TOGBR1, 0x0155);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
424
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
425 #if (ANLG_FAM == 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
426 // This transmission disables Band gap fast mode Enable BB charge.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
427 ABB_WriteRegister(VRPCCTL2, 0x1fc);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
428
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
429 /* *********** DC/DC enabling selection ************************************************************** */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
430 // This transmission changes the register page in OMEGA for usp to pg1.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
431 ABB_SetPage(PAGE1);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
432
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
433 /* Insert here accesses to modify DC/DC parameters. Default is a switching frequency of 240 Khz */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
434 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
435 SYS_UWORD8 vrpcctrl3_data;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
436
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
437 #if (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
438 vrpcctrl3_data = 0x007d; // core voltage 1.4V for C035
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
439 #else
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
440 vrpcctrl3_data = 0x00bd; // core voltage 1.8V for C05
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
441 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
442
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
443 if(modules & DCDC) // check if the DCDC is enabled
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
444 {
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
445 vrpcctrl3_data |= 0x0002; // set DCDCEN
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
446 }
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
447
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
448 // This access disables the DCDC.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
449 ABB_WriteRegister(VRPCCTRL3, vrpcctrl3_data);
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
450 }
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
451
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
452 /* ************************ SELECTION OF TEST MODE FOR ABB **************************************** */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
453 /* This test configuration allows visibility on BULENA,BULON,BDLON,BDLENA on test pins */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
454 /* ***************************************************************************************************/
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
455 #if (BOARD==6)&& (ANLG_FAM==1) //BUG01967 to remove access to TAPCTRL (EVA4 board and Nausica)
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
456 // This transmission enables Omega test register.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
457 ABB_WriteRegister(TAPCTRL, 0x01);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
458
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
459 // This transmission select Omega test instruction.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
460 ABB_WriteRegister(TAPREG, TSPTEST1);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
461
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
462 // This transmission disables Omega test register.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
463 ABB_WriteRegister(TAPCTRL, 0x00);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
464 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
465 /* *************************************************************************************************** */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
466
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
467 if (!bRecoveryFlag) // Check recovery status from L1, prevent G23 SIM issue
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
468 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
469 // This transmission changes SIM power supply to 3 volts.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
470 ABB_WriteRegister(VRPCCTRL1, 0x45);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
471 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
472
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
473 ABB_SetPage(PAGE0);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
474
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
475 // This transmission enables selected OMEGA modules.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
476 ABB_WriteRegister(TOGBR1, (modules & ~DCDC) >> 6);
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
477
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
478 if(modules & MADC) // check if the ADC is enabled
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
479 {
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
480 // This transmission connects the resistive divider to MB and BB.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
481 ABB_WriteRegister(BCICTL1, 0x0005);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
482 }
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
483 #elif ((ANLG_FAM == 2) || (ANLG_FAM == 3))
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
484 // Restore the ABB checks and debouncing if start on TESTRESETZ
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
485
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
486 // This transmission changes the register page in the ABB for usp to pg1.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
487 ABB_SetPage(PAGE1);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
488
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
489 // This transmission sets the AFCCK to CKIN/2.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
490 ABB_WriteRegister(AFCCTLADD, 0x01);
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
491
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
492 // This transmission enables the tapreg.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
493 ABB_WriteRegister(TAPCTRL, 0x01);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
494
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
495 // This transmission enables access to page 2.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
496 ABB_WriteRegister(TAPREG, 0x01b);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
497
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
498 // This transmission changes the register page in the ABB for usp to pg2.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
499 ABB_SetPage(PAGE2);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
500
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
501 #if (ANLG_FAM == 2)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
502 // Restore push button environment
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
503 ABB_WriteRegister(0x3C, 0x07);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
504
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
505 #elif (ANLG_FAM == 3)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
506
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
507 // Restore push button environment
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
508 ABB_WriteRegister(0x3C, 0xBF);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
509
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
510 /* ************************ SELECTION OF BBCFG CONFIG FOR ABB 3 PG1_0 *******************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
511 #if (ANLG_PG == S_PG_10) // SYREN PG1.0 ON ESAMPLE
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
512 ABB_WriteRegister(BBCFG, C_BBCFG); // Initialize transmit register
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
513 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
514 // This transmission enables access to page 0.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
515 ABB_SetPage(PAGE0);
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
516
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
517 // reset bit MSKINT1 , if set by TESTRESET
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
518 reg=ABB_ReadRegister(VRPCSTS) & 0xffe;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
519
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
520 ABB_WriteRegister(VRPCSTS, reg);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
521
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
522 ABB_SetPage(PAGE2);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
523
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
524 // Restore default for BG behavior in sleep mode
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
525 ABB_WriteRegister(VRPCAUX, 0xBF);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
526
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
527 // Restore default for deboucing length
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
528 ABB_WriteRegister(VRPCLDO, 0x00F);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
529
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
530 // Restore default for INT1 generation, wait time in switch on, checks in switch on
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
531 ABB_WriteRegister(VRPCABBTST, 0x0002);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
532
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
533 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
534
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
535 // This transmission changes the register page in the ABB for usp to pg1.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
536 ABB_SetPage(PAGE1);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
537
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
538 // This transmission sets tapinst to id code.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
539 ABB_WriteRegister(TAPREG, 0x0001);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
540
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
541 // This transmission disables TAPREG access.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
542 ABB_WriteRegister(TAPCTRL, 0x00);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
543
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
544 // enable BB battery charge BCICONF register, enable test mode to track BDLEN and BULEN windows
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
545 // This transmission enables BB charge and BB bridge connection for BB measurements.
327
d7b25dca1266 .../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
546 #if ENABLE_BACKUP_BATTERY
d7b25dca1266 .../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
547 ABB_WriteRegister(BCICONF, 0x060);
d7b25dca1266 .../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
548 #else
d7b25dca1266 .../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
549 ABB_WriteRegister(BCICONF, 0x000);
d7b25dca1266 .../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
550 #endif
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
551
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
552 /* ************************ SELECTION OF BBCFG CONFIG FOR ABB 3 PG2_0 *******************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
553 #if (ANLG_FAM == 3)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
554 #if (ANLG_PG == S_PG_20) // SYREN PG2.0 ON EVACONSO
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
555 ABB_WriteRegister(BBCFG, C_BBCFG); // Initialize transmit register
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
556 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
557 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
558
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
559 /* ************************ SELECTION OF TEST MODE FOR ABB ******************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
560 /* This test configuration allows visibility on test pins TAPCTRL has not to be reset */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
561 /* ****************************************************************************************************/
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
562
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
563 // This transmission enables the tapreg.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
564 ABB_WriteRegister(TAPCTRL, 0x01);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
565
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
566 // This transmission select ABB test instruction.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
567 ABB_WriteRegister(TAPREG, TSPEN);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
568
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
569 // This transmission changes the register page in ABB for usp to pg0.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
570 ABB_SetPage(PAGE0);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
571
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
572 // This transmission enables selected ABB modules.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
573 ABB_WriteRegister(TOGBR1, modules >> 6);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
574
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
575 // enable MB & BB resistive bridges for measurements
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
576 if(modules & MADC) // check if the ADC is enabled
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
577 {
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
578 // This transmission connects the resistive divider to MB and BB.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
579 ABB_WriteRegister(BCICTL1, 0x0001);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
580 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
581
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
582 /********* Sleep definition part ******************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
583 // This transmission changes the register page in the ABB for usp to pg1.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
584 #if (ANLG_FAM == 2)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
585 ABB_SetPage(PAGE1);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
586
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
587 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
588 reg = ABB_ReadRegister(VRPCCFG) & 0x1e0;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
589
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
590 ABB_WriteRegister(VRPCCFG, (SLPDLY | reg));
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
591
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
592 // update the ABB mask sleep register (regulator disabled in deep sleep), and clear previous mask value.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
593 reg = ABB_ReadRegister(VRPCMSK) & 0x1e0;
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
594 ABB_WriteRegister(VRPCMSK, (MASK_SLEEP_MODE | reg));
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
595 #elif (ANLG_FAM == 3)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
596 Syren_Sleep_Config(NORMAL_SLEEP,SLEEP_BG,SLPDLY);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
597 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
598 // This transmission changes the register page in the ABB for usp to pg0.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
599 ABB_SetPage(PAGE0);
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
600 #endif
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
601
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
602 // SW workaround for initialization of the audio parts of the ABB to avoid white noise
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
603 // C.f. BUG1941
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
604 // Set VDLR and VULR bits
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
605 // Write TOGBR1 register
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
606 // This transmission enables selected ABB modules.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
607 ABB_WriteRegister(TOGBR1, 0x0A);
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
608
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
609 // wait for 1 ms
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
610 wait_ARM_cycles(convert_nanosec_to_cycles(1000000));
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
611
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
612 // Reset VDLS and VULS bits
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
613 // Write TOGBR1 register
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
614 // This transmission enables selected ABB modules.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
615 ABB_WriteRegister(TOGBR1, 0x05);
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
616
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
617 // Stop the SPI clock
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
618 #ifdef SPI_CLK_LOW_POWER
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
619 SPI_CLK_DISABLE
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
620 #endif
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
621
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
622 #if (ABB_SEMAPHORE_PROTECTION == 3)
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
623 // release the semaphore only if it has correctly been created.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
624 if(sem_status == NU_SUCCESS)
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
625 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
626 NU_Release_Semaphore(&abb_sem);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
627 }
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
628 #endif // ABB_SEMAPHORE_PROTECTION
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
629 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
630
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
631
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
632 /*-----------------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
633 /* ABB_Read_ADC() */
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
634 /* */
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
635 /* This function manages all the spi serial transfer to read all the */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
636 /* ABB ADC conversion channels. */
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
637 /* Stores the result in Buff parameter. */
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
638 /* */
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
639 /*-----------------------------------------------------------------------*/
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
640 void ABB_Read_ADC(SYS_UWORD16 *Buff)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
641 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
642 volatile SYS_UWORD16 status;
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
643 STATUS sem_status;
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
644
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
645 #if (ABB_SEMAPHORE_PROTECTION == 3)
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
646
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
647 // check if the semaphore has been correctly created and try to obtain it.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
648 // if the semaphore cannot be obtained, the task is suspended and then resumed
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
649 // as soon as the semaphore is released.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
650
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
651 sem_status = NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND);
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
652
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
653 #endif // ABB_SEMAPHORE_PROTECTION
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
654
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
655 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags.
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
656 SPI_Ready_for_RDWR
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
657 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
658
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
659 // This transmission changes the register page in the ABB for usp to pg0.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
660 ABB_SetPage(PAGE0);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
661
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
662 /* Read all ABB ADC registers */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
663 *Buff++ = ABB_ReadRegister(VBATREG);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
664 *Buff++ = ABB_ReadRegister(VCHGREG);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
665 *Buff++ = ABB_ReadRegister(ICHGREG);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
666 *Buff++ = ABB_ReadRegister(VBKPREG);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
667 *Buff++ = ABB_ReadRegister(ADIN1REG);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
668 *Buff++ = ABB_ReadRegister(ADIN2REG);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
669 *Buff++ = ABB_ReadRegister(ADIN3REG);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
670
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
671 #if (ANLG_FAM == 1)
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
672 *Buff++ = ABB_ReadRegister(ADIN4XREG);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
673 *Buff++ = ABB_ReadRegister(ADIN5YREG);
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
674 #elif (ANLG_FAM == 2)
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
675 *Buff++ = ABB_ReadRegister(ADIN4REG);
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
676 #elif (ANLG_FAM == 3)
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
677 *Buff++ = ABB_ReadRegister(ADIN4REG);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
678 *Buff++ = ABB_ReadRegister(ADIN5REG);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
679 #endif // ANLG_FAM
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
680
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
681 // Stop the SPI clock
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
682 #ifdef SPI_CLK_LOW_POWER
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
683 SPI_CLK_DISABLE
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
684 #endif
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
685
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
686 #if (ABB_SEMAPHORE_PROTECTION == 3)
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
687 // release the semaphore only if it has correctly been created.
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
688 if(sem_status == NU_SUCCESS)
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
689 {
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
690 NU_Release_Semaphore(&abb_sem);
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
691 }
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
692 #endif // ABB_SEMAPHORE_PROTECTION
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
693 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
694
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
695
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
696 /*-----------------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
697 /* ABB_Conf_ADC() */
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
698 /* */
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
699 /* This function manages all the spi serial transfer to: */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
700 /* - select the ABB ADC channels to be converted */
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
701 /* - enable/disable EOC interrupt */
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
702 /* */
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
703 /*-----------------------------------------------------------------------*/
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
704 void ABB_Conf_ADC(SYS_UWORD16 Channels, SYS_UWORD16 ItVal)
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
705 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
706 volatile SYS_UWORD16 status;
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
707 STATUS sem_status;
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
708 SYS_UWORD16 reg_val;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
709
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
710 #if (ABB_SEMAPHORE_PROTECTION == 3)
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
711
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
712 // check if the semaphore has been correctly created and try to obtain it.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
713 // if the semaphore cannot be obtained, the task is suspended and then resumed
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
714 // as soon as the semaphore is released.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
715
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
716 sem_status = NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND);
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
717
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
718 #endif // ABB_SEMAPHORE_PROTECTION
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
719
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
720 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags.
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
721 SPI_Ready_for_RDWR
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
722 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
723
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
724 // This transmission changes the register page in the ABB for usp to pg0.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
725 ABB_SetPage(PAGE0);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
726
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
727 /* select ADC channels to be converted */
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
728 #if (ANLG_FAM == 1)
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
729 ABB_WriteRegister(MADCCTRL1, Channels);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
730 #elif ((ANLG_FAM == 2) || (ANLG_FAM == 3))
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
731 ABB_WriteRegister(MADCCTRL, Channels);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
732 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
733
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
734 reg_val = ABB_ReadRegister(ITMASK);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
735
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
736 // This transmission configure the End Of Conversion IT without modifying other bits in the same register.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
737 if(ItVal == EOC_INTENA)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
738 ABB_WriteRegister(ITMASK, reg_val & EOC_INTENA);
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
739 else if(ItVal == EOC_INTMASK)
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
740 ABB_WriteRegister(ITMASK, reg_val | EOC_INTMASK);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
741
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
742 // Stop the SPI clock
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
743 #ifdef SPI_CLK_LOW_POWER
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
744 SPI_CLK_DISABLE
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
745 #endif
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
746
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
747 #if (ABB_SEMAPHORE_PROTECTION == 3)
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
748 // release the semaphore only if it has correctly been created.
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
749 if(sem_status == NU_SUCCESS)
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
750 {
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
751 NU_Release_Semaphore(&abb_sem);
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
752 }
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
753 #endif // ABB_SEMAPHORE_PROTECTION
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
754 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
755
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
756
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
757 /*------------------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
758 /* ABB_sleep() */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
759 /* */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
760 /* This function disables the DCDC and returns to PAGE 0. It stops then */
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
761 /* the 13MHz clock in ABB. A wait loop s required to allow */
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
762 /* first slow access to ABB clock register. */
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
763 /* */
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
764 /* WARNING !! : this function must not be protected by semaphore !! */
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
765 /* */
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
766 /* Returns AFC value. */
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
767 /* */
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
768 /*------------------------------------------------------------------------*/
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
769 SYS_UWORD32 ABB_sleep(SYS_UWORD8 sleep_performed, SYS_WORD16 afc)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
770 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
771 volatile SYS_UWORD16 status;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
772 SYS_UWORD32 afcout_index;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
773 volatile SYS_UWORD16 nb_it;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
774 SYS_UWORD16 reg_val;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
775
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
776 // table for AFC allowed values during Sleep mode. First 5th elements
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
777 // are related to positive AFC values, last 5th to negative ones.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
778 SYS_UWORD32 Afcout_T[10]= {0x0f,0x1f,0x3f,0x7f,0xff,0x00,0x01,0x03,0x07,0x0f};
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
779
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
780 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags.
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
781 SPI_Ready_for_RDWR
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
782 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
783
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
784 // COMPUTATION AND PROGRAMMING OF AFC VALUE
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
785 //---------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
786 if(afc & 0x1000)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
787 afcout_index = ((afc + 512)>>10) + 1;
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
788 else
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
789 afcout_index = (afc + 512)>>10;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
790
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
791 if (sleep_performed == FRAME_STOP) // Big sleep
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
792 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
793 #if ((ANLG_FAM == 2) || (ANLG_FAM == 3))
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
794 //////////// ADD HERE IOTA or SYREN CONFIGURATION FOR BIG SLEEP ////////////////////////////
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
795 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
796
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
797 }
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
798 else // Deep sleep
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
799 {
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
800 #if(ANLG_FAM == 1)
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
801 // SELECTION OF AFC TEST MODE FOR OMEGA
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
802 //---------------------------------------------------
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
803 // This test configuration allows access on the AFCOUT register
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
804 ABB_SetPage(PAGE1);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
805
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
806 // This transmission enables OMEGA test register.
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
807 ABB_WriteRegister(TAPCTRL, 0x01);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
808
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
809 // This transmission selects OMEGA test instruction.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
810 ABB_WriteRegister(TAPREG, AFCTEST);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
811
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
812 // Set AFCOUT to 0.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
813 ABB_WriteRegister(AFCOUT, 0x00 >> 6);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
814
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
815 ABB_SetPage(PAGE0);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
816
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
817 #elif (ANLG_FAM == 2)
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
818 // This configuration allows access on the AFCOUT register
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
819 ABB_SetPage(PAGE1);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
820
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
821 // Read AFCCTLADD value and enable USP access to AFCOUT register
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
822 reg_val = (ABB_ReadRegister(AFCCTLADD) | 0x04);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
823
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
824 ABB_WriteRegister(AFCCTLADD, reg_val);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
825
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
826 // Set AFCOUT to 0.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
827 ABB_WriteRegister(AFCOUT, 0x00);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
828
327
d7b25dca1266 .../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
829 #if ENABLE_BACKUP_BATTERY
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
830 // Read BCICONF value and cut the measurement bridge of BB cut the BB charge.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
831 reg_val = ABB_ReadRegister(BCICONF) & 0x039f;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
832
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
833 ABB_WriteRegister(BCICONF, reg_val);
327
d7b25dca1266 .../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
834 #endif
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
835
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
836 // Disable the ABB test mode
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
837 ABB_WriteRegister(TAPCTRL, 0x00);
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
838
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
839 ABB_SetPage(PAGE0);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
840
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
841 // Read BCICTL1 value and cut the measurement bridge of MB.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
842 reg_val = ABB_ReadRegister(BCICTL1) & 0x03fe;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
843
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
844 ABB_WriteRegister(BCICTL1, reg_val);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
845 #endif
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
846
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
847 #if (ANLG_FAM == 3) // Nothing to be done as MB and BB measurement bridges are automatically disconnected
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
848 // in Syren during sleep mode. BB charge stays enabled
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
849 ABB_SetPage(PAGE1); // Initialize transmit reg_num. This transmission
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
850 // change the register page in IOTA for usp to pg1
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
851
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
852 ABB_WriteRegister(TAPCTRL, 0x00); // Disable Syren test mode
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
853
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
854 ABB_SetPage(PAGE0);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
855 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
856
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
857 // switch off MADC, AFC, AUXDAC, VOICE.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
858 ABB_WriteRegister(TOGBR1, 0x155);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
859
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
860 // Switch off Analog supply LDO
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
861 //-----------------------------
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
862 #if (ANLG_FAM == 1)
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
863 ABB_SetPage(PAGE1);
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
864
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
865 // Read VRPCCTL3 register value and switch off VR3.
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
866 reg_val = ABB_ReadRegister(VRPCCTRL3) & 0x3df;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
867
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
868 ABB_WriteRegister(VRPCCTRL3, reg_val);
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
869
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
870 #elif (ANLG_FAM == 2)
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
871 // Read VRPCSTS register value and extract status of meaningfull inputs.
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
872 reg_val = ABB_ReadRegister(VRPCSTS) & 0x0070;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
873
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
874 #ifdef ABB_SLEEP_RESTRICTION
648
337e6d3a4454 abb.c: disable superdeep sleep on Luna
Mychaela Falconia <falcon@freecalypso.org>
parents: 327
diff changeset
875 if (reg_val == 0x30 && ABB_sleep_allowed)
337e6d3a4454 abb.c: disable superdeep sleep on Luna
Mychaela Falconia <falcon@freecalypso.org>
parents: 327
diff changeset
876 #else
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
877 if (reg_val == 0x30)
648
337e6d3a4454 abb.c: disable superdeep sleep on Luna
Mychaela Falconia <falcon@freecalypso.org>
parents: 327
diff changeset
878 #endif
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
879 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
880 // start the SLPDLY counter in order to switch the ABB in sleep mode. This transmission sets IOTA sleep bit.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
881 ABB_WriteRegister(VRPCDEV, 0x02);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
882 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
883
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
884 // Dummy transmission to clean of ABB bus. This transmission accesses IOTA address 0 in "read".
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
885 ABB_WriteRegister(0x0000 | 0x0001, 0x0000);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
886
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
887 #elif (ANLG_FAM == 3)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
888 // In Syren there is no need to check for VRPCCFG as wake up prioritys are changed
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
889 // start the SLPDLY counter in order to switch the ABB in sleep mode
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
890 ABB_WriteRegister(VRPCDEV,0x02); // Initialize transmit reg_num. This transmission
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
891 // set Syren sleep bit
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
892 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
893 // Dummy transmission to clean of ABB bus. This transmission accesses SYREN address 0 in "read".
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
894 ABB_WriteRegister(0x0000 | 0x0001, 0x0000);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
895 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
896 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
897
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
898 // Switch to low frequency clock
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
899 ABB_stop_13M();
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
900 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
901
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
902 // Stop the SPI clock
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
903 #ifdef SPI_CLK_LOW_POWER
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
904 SPI_CLK_DISABLE
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
905 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
906
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
907 #if (OP_L1_STANDALONE == 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
908 #if (CHIPSET == 12)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
909 // GPIO_InitAllPull(ALL_ONE); // enable all GPIO internal pull
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
910 // workaround to set APLL_DIV_CLK( internal PU) at high level
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
911 // by default APLL_DIV_CLK is low pulling 80uA on VRIO
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
912 // *(SYS_UWORD16*) (0xFFFFFD90)= 0x01;//CNTL_APLL_DIV_CLK -> APLL_CLK_DIV != 0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
913 // *(SYS_UWORD16*) (0xFFFEF030)= 0x10;// DPLL mode
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
914 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
915 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
916 return(Afcout_T[afcout_index]);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
917 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
918
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
919
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
920 /*------------------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
921 /* ABB_wakeup() */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
922 /* */
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
923 /* This function sets the 13MHz clock working in ABB. A wait loop */
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
924 /* is required to allow first slow access to ABB clock register. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
925 /* Then it re-enables DCDC and returns to PAGE 0. */
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
926 /* */
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
927 /* WARNING !! : this function must not be protected by semaphore !! */
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
928 /* */
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
929 /*------------------------------------------------------------------------*/
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
930 void ABB_wakeup(SYS_UWORD8 sleep_performed, SYS_WORD16 afc)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
931 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
932 volatile SYS_UWORD16 status;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
933 SYS_UWORD16 reg_val;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
934
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
935 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags.
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
936 SPI_Ready_for_RDWR
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
937 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
938
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
939 if (sleep_performed == FRAME_STOP) // Big sleep
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
940 {
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
941 #if ((ANLG_FAM == 2) || (ANLG_FAM == 3))
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
942 //////////// ADD HERE IOTA or SYREN CONFIGURATION FOR BIG SLEEP WAKEUP ////////////////////////////
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
943 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
944 }
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
945 else // Deep sleep
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
946 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
947 #if (OP_L1_STANDALONE == 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
948 #if (CHIPSET == 12)
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
949 // restore context from
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
950 // workaround to set APLL_DIV_CLK( internal PU) at high level
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
951 // by default APLL_DIV_CLK is low pulling 80uA on VRIO
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
952 // *(SYS_UWORD16*) (0xFFFFFD90)= 0x00;//CNTL_APLL_DIV_CLK -> APLL_DIV_CLK != 0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
953 // *(SYS_UWORD16*) (0xFFFEF030)= 0x00;// DPLL mode
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
954 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
955 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
956
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
957 // Restitutes 13MHZ Clock to ABB
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
958 ABB_free_13M();
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
959
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
960 // Switch ON Analog supply LDO
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
961 #if (ANLG_FAM == 1)
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
962 ABB_SetPage(PAGE1);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
963
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
964 // Read VRPCCTL3 register value and switch on VR3.
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
965 reg_val = ABB_ReadRegister(VRPCCTRL3) | 0x020;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
966
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
967 ABB_WriteRegister(VRPCCTRL3, reg_val);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
968 ABB_SetPage(PAGE0);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
969 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
970
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
971 // This transmission switches on MADC, AFC.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
972 ABB_WriteRegister(TOGBR1, 0x280);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
973
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
974 // This transmission sets the AUXAFC2.
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
975 ABB_WriteRegister(AUXAFC2, ((afc>>10) & 0x7));
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
976
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
977 // This transmission sets the AUXAFC1.
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
978 ABB_WriteRegister(AUXAFC1, (afc & 0x3ff));
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
979
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
980 #if (ANLG_FAM == 1)
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
981 // Remove AFC test mode
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
982 ABB_SetPage(PAGE1);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
983
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
984 // This transmission select Omega test instruction.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
985 ABB_WriteRegister(TAPREG, TSPTEST1);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
986
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
987 // Disable test mode selection
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
988 // This transmission disables Omega test register.
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
989 ABB_WriteRegister(TAPCTRL, 0x00 >> 6);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
990
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
991 ABB_SetPage(PAGE0);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
992
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
993 #elif (ANLG_FAM == 2)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
994 ABB_SetPage(PAGE1);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
995
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
996 // Read AFCCTLADD register value and disable USP access to AFCOUT register.
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
997 reg_val = ABB_ReadRegister(AFCCTLADD) & ~0x04;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
998
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
999 ABB_WriteRegister(AFCCTLADD, reg_val);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1000
327
d7b25dca1266 .../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1001 #if ENABLE_BACKUP_BATTERY
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1002 // Read BCICONF register value and enable BB measurement bridge enable BB charge.
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1003 reg_val = ABB_ReadRegister(BCICONF) | 0x0060;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1004
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1005 ABB_WriteRegister(BCICONF, reg_val);
327
d7b25dca1266 .../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1006 #endif
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1007
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1008
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1009 /* *************************************************************************************************** */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1010 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1011 reg_val = ABB_ReadRegister(VRPCCFG) & 0x1e0;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1012 ABB_WriteRegister(VRPCCFG, (SLPDLY | reg_val));
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1013
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1014 // Enable the ABB test mode
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1015 ABB_WriteRegister(TAPCTRL, 0x01);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1016 ABB_WriteRegister(TAPREG, TSPEN);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1017 ABB_SetPage(PAGE0);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1018
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1019 // Read BCICTL1 register value and enable MB measurement bridge and cut the measurement bridge of MB.
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1020 reg_val = ABB_ReadRegister(BCICTL1) | 0x0001;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1021
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1022 ABB_WriteRegister(BCICTL1, reg_val);
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1023 #endif
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1024
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1025 #if (ANLG_FAM == 3)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1026
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1027 ABB_SetPage(PAGE1);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1028
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1029 /* *************************************************************************************************** */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1030 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1031 reg_val = ABB_ReadRegister(VRPCCFG) & 0x1e0;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1032 ABB_WriteRegister(VRPCCFG, (SLPDLY | reg_val));
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1033
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1034 /* ************************ SELECTION OF TEST MODE FOR ABB=3 *****************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1035 /* This test configuration allows visibility on test pins TAPCTRL has not to be reset */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1036 /* ****************************************************************************************************/
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1037
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1038 ABB_WriteRegister(TAPCTRL, 0x01); // Initialize the transmit register
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1039 // This transmission enables IOTA test register
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1040
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1041 ABB_WriteRegister(TAPREG, TSPEN);
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1042 // This transmission select IOTA test instruction
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1043 // This transmission select IOTA test instruction
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1044 /**************************************************************************************************** */
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1045
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1046 ABB_SetPage(PAGE0); // Initialize transmit reg_num. This transmission
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1047 #endif
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1048 }
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1049
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1050 // Stop the SPI clock
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1051 #ifdef SPI_CLK_LOW_POWER
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1052 SPI_CLK_DISABLE
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1053 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1054 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1055
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1056 /*------------------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1057 /* ABB_wa_VRPC() */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1058 /* */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1059 /* This function initializes the VRPCCTRL1 or VRPCSIM register */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1060 /* according to the ABB used. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1061 /* */
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1062 /*------------------------------------------------------------------------*/
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1063 void ABB_wa_VRPC(SYS_UWORD16 value)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1064 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1065 volatile SYS_UWORD16 status;
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1066 STATUS sem_status;
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1067
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1068 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3))
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1069
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1070 // check if the semaphore has been correctly created and try to obtain it.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1071 // if the semaphore cannot be obtained, the task is suspended and then resumed
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1072 // as soon as the semaphore is released.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1073
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1074 sem_status = NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND);
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1075
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1076 #endif // ABB_SEMAPHORE_PROTECTION
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1077
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1078 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags.
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1079 SPI_Ready_for_WR
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1080 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1081
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1082 ABB_SetPage(PAGE1);
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1083
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1084 #if (ANLG_FAM == 1)
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1085 // This transmission initializes the VRPCCTL1 register.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1086 ABB_WriteRegister(VRPCCTRL1, value);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1087
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1088 #elif (ANLG_FAM == 2)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1089 // This transmission initializes the VRPCSIM register.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1090 ABB_WriteRegister(VRPCSIM, value);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1091
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1092 #elif (ANLG_FAM == 3)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1093 // This transmission initializes the VRPCSIMR register.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1094 ABB_WriteRegister(VRPCSIMR, value);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1095
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1096 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1097
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1098 ABB_SetPage(PAGE0);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1099
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1100 // Stop the SPI clock
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1101 #ifdef SPI_CLK_LOW_POWER
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1102 SPI_CLK_DISABLE
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1103 #endif
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1104
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1105 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3))
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1106 // release the semaphore only if it has correctly been created.
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1107 if(sem_status == NU_SUCCESS)
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1108 {
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1109 NU_Release_Semaphore(&abb_sem);
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1110 }
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1111 #endif // ABB_SEMAPHORE_PROTECTION
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1112 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1113
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1114
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1115 /*-----------------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1116 /* ABB_Write_Uplink_Data() */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1117 /* */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1118 /* This function uses the SPI to write to ABB uplink buffer. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1119 /* */
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1120 /*-----------------------------------------------------------------------*/
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1121 void ABB_Write_Uplink_Data(SYS_UWORD16 *TM_ul_data)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1122 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1123 SYS_UWORD8 i;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1124 volatile SYS_UWORD16 status;
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1125 STATUS sem_status;
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1126
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1127 #if ((ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3))
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1128
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1129 // check if the semaphore has been correctly created and try to obtain it.
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1130 // if the semaphore cannot be obtained, the task is suspended and then resumed
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1131 // as soon as the semaphore is released.
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1132
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1133 sem_status = NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND);
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1134
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1135 #endif // ABB_SEMAPHORE_PROTECTION
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1136
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1137 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags.
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1138 SPI_Ready_for_WR
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1139 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1140
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1141 // Select Page 0 for TOGBR2
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1142 ABB_SetPage(PAGE0);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1143
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1144 // Initialize pointer of burst buffer 1 : IBUFPTR is bit 10 of TOGBR2
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1145 ABB_WriteRegister(TOGBR2, 0x10);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1146
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1147 // Clear, assuming that it works like IBUFPTR of Vega
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1148 ABB_WriteRegister(TOGBR2, 0x0);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1149
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1150 // Write the ramp data
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1151 for (i=0;i<16;i++)
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1152 ABB_WriteRegister(BULDATA1_2, TM_ul_data[i]>>6);
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1153
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1154 // Stop the SPI clock
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1155 #ifdef SPI_CLK_LOW_POWER
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1156 SPI_CLK_DISABLE
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1157 #endif
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1158
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1159 #if ((ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3))
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1160 // release the semaphore only if it has correctly been created.
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1161 if(sem_status == NU_SUCCESS)
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1162 {
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1163 NU_Release_Semaphore(&abb_sem);
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1164 }
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1165 #endif // ABB_SEMAPHORE_PROTECTION
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1166 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1167
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1168 //////////////////////// IDEV-INLO integration of sleep mode for Syren ///////////////////////////////////////
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1169
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1170 #if (ANLG_FAM == 3)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1171
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1172 // Syren Sleep configuration function --------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1173 void Syren_Sleep_Config(SYS_UWORD16 sleep_type,SYS_UWORD16 bg_select, SYS_UWORD16 sleep_delay)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1174 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1175 volatile SYS_UWORD16 status,sl_ldo_stat;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1176
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1177 ABB_SetPage(PAGE1); // Initialize transmit register. This transmission
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1178 // change the register page in ABB for usp to pg1
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1179
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1180 ABB_WriteRegister(VRPCCFG, sleep_delay); // write delay value
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1181
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1182 sl_ldo_stat = ((sleep_type<<9|bg_select<<8) & 0x0374);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1183
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1184 ABB_WriteRegister(VRPCMSKSLP, sl_ldo_stat); // write sleep ldo configuration
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1185
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1186 ABB_SetPage(PAGE0); // Initialize transmit register. This transmission
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1187 // change the register page in ABB for usp to pg0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1188 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1189 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1190
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1191
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1192 #if (OP_L1_STANDALONE == 0)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1193 /*-----------------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1194 /* ABB_Power_Off() */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1195 /* */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1196 /* This function uses the SPI to switch off the ABB. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1197 /* */
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1198 /*-----------------------------------------------------------------------*/
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1199 void ABB_Power_Off(void)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1200 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1201 // Wait until all necessary actions are performed (write in FFS, etc...) to power-off the board (empirical value - 30 ticks).
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1202 NU_Sleep (30);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1203
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1204 // Wait also until <ON/OFF> key is released.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1205 // This is needed to avoid, if the power key is pressed for a long time, to switch
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1206 // ON-switch OFF the mobile, until the power key is released.
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1207 #if((ANLG_FAM == 1) || (ANLG_FAM == 2))
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1208 while ((ABB_Read_Status() & ONREFLT) == PWR_OFF_KEY_PRESSED) {
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1209 #elif(ANLG_FAM == 3)
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1210 while ((ABB_Read_Register_on_page(PAGE1, VRPCCFG) & PWOND) == PWR_OFF_KEY_PRESSED) {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1211 #endif
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1212
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1213 NU_Sleep (1); }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1214
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1215 BZ_KeyBeep_OFF();
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1216
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1217 #if(ANLG_FAM == 1)
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1218 ABB_Write_Register_on_page(PAGE0, VRPCCTL2, 0x00EE);
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1219 #elif((ANLG_FAM == 2) || (ANLG_FAM == 3))
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1220 ABB_Write_Register_on_page(PAGE0, VRPCDEV, 0x0001);
698
4f458e31b6e1 .../drv_core/abb/abb.[ch]: sync with Tourmaline
Mychaela Falconia <falcon@freecalypso.org>
parents: 648
diff changeset
1221 #endif
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1222 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1223 #endif