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annotate blobs/patches/main-pirelli.patch @ 605:07d0dc4431f4

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bootloader.s: same MEMIF fix as in int.s plus DPLL BYPASS fix Both MEMIF and DPLL settings are now the same between int.s and bootloader.s assembly code paths. Previously bootloader.s was setting DPLL BYPASS /2 mode, which persisted until _INT_Initialize code with the bootloader body omitted, or was changed to /1 in the hardware init function in the bootloader.lib:start.obj module.
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 17 Jun 2019 18:40:32 +0000 (2019-06-17)
parents 8dd671b7d41e
children
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8dd671b7d41e blobs/patches: main-pirelli and main-rvtmodem patches added
Mychaela Falconia <falcon@freecalypso.org>
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1 # This patch applies to the Init_Target() function in the init.obj module in
8dd671b7d41e blobs/patches: main-pirelli and main-rvtmodem patches added
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2 # main.lib; the present version is for making TCS211 run on the Pirelli.
8dd671b7d41e blobs/patches: main-pirelli and main-rvtmodem patches added
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3 # This patch sets the same memory and peripheral chip select timings and
8dd671b7d41e blobs/patches: main-pirelli and main-rvtmodem patches added
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4 # widths as Pirelli's fw.
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6 [init.obj]
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8 # value goes into nCS0, nCS1 and nCS3 config registers
8dd671b7d41e blobs/patches: main-pirelli and main-rvtmodem patches added
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9 .text 66 A4
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10 # the nCS2 setting in our original blob is already correct for the Pirelli
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12 # value goes into nCS4 config reg
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13 .text 72 A7
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15 # nop out the write into 0x02700000
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17 .text 128 C0
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18 .text 129 46