*** Log of decoded RVT output ***
2015-05-16 (gmtime):
[02:38:25] Warning: Rx 1 byte outside of a packet
[02:38:25] RV 00000000 0 ^@^@^@^@
[02:38:25] RV 00000000 1 RVT: Lost Message 04000017
[02:38:25] RV 00010001 5 RVM: Created task nb  0x00000001
[02:38:25] RV 00010001 5 RVM: Resumed task nb  0x00000001
[02:38:25] RV 00010001 5 RVM: Resumed SWE  0x00010002
[02:38:25] RV 00010001 5 RVM: SWE initialization success
[02:38:25] RV 00010001 3 create_RVtasks: RVT (0x00010002) started
[02:38:25] RV 00010001 5 RVM: SWE START REQUEST 0x000A0004
[02:38:25] RV 00010001 2 rvm.SweHndlr.resolve_t2_grouping(), SWE Not type 2:  0x000A0004
[02:38:25] RV 00010001 3 RVM: SWE list built success
[02:38:25] RV 00010001 3 RVM: trying to launch SWE 0x000A0004
[02:38:25] RV 00010001 5 RVM: SWE memory bank allocation success
[02:38:25] RV 00010001 5 RVM: SWE set info functions called
[02:38:25] RV 00010001 5 RVM: Created task nb  0x00000002
[02:38:25] RV 00010001 5 RVM: Resumed task nb  0x00000002
[02:38:25] RV 00010001 5 RVM: Resumed SWE  0x000A0004
[02:38:25] RV 00010001 5 RVM: SWE initialization success
[02:38:25] RV 00010001 3 create_RVtasks: FFS (0x000a0004) started
[02:38:25] RV 00010001 5 RVM: SWE START REQUEST 0x000A0010
[02:38:25] RV 00010001 2 rvm.SweHndlr.resolve_t2_grouping(), SWE Not type 2:  0x000A0010
[02:38:25] RV 00010001 3 RVM: SWE list built success
[02:38:25] RV 00010001 3 RVM: trying to launch SWE 0x000A0010
[02:38:25] RV 00010001 5 RVM: SWE memory bank allocation success
[02:38:25] RV 000A0010 5 SPI : spi_set_info: try to init GLOBAL INFO SPI structure ... 
[02:38:25] RV 00010001 5 RVM: SWE set info functions called
[02:38:25] RV 00010001 5 RVM: Created task nb  0x00000003
[02:38:25] RV 000A0010 5 SPI_task: Initialization
[02:38:25] RV 00010001 5 RVM: Resumed task nb  0x00000003
[02:38:25] RV 00010001 5 RVM: Resumed SWE  0x000A0010
[02:38:25] RV 00010001 5 RVM: SWE initialization success
[02:38:25] RV 00010001 3 create_RVtasks: SPI (0x000a0010) started
[02:38:25] RV 00010001 5 RVM: SWE START REQUEST 0x001E0004
[02:38:25] RV 00010001 2 rvm.SweHndlr.resolve_t2_grouping(), SWE Not type 2:  0x001E0004
[02:38:25] RV 00010001 3 RVM: SWE list built success
[02:38:25] RV 00010001 3 RVM: trying to launch SWE 0x001E0004
[02:38:25] RV 00010001 5 RVM: SWE memory bank allocation success
[02:38:25] RV 00010001 5 RVM: SWE set info functions called
[02:38:25] RV 00010001 5 RVM: Created task nb  0x00000004
[02:38:25] RV 00010001 5 RVM: Resumed task nb  0x00000004
[02:38:25] RV 00010001 5 RVM: Resumed SWE  0x001E0004
[02:38:25] RV 00010001 5 RVM: SWE initialization success
[02:38:25] RV 00010001 3 create_RVtasks: ETM (0x001e0004) started
[02:38:25] RV 00010001 5 RVM: SWE START REQUEST 0x000A0002
[02:38:25] RV 00010001 2 rvm.SweHndlr.resolve_t2_grouping(), SWE Not type 2:  0x000A0002
[02:38:25] RV 00010001 3 RVM: SWE list built success
[02:38:25] RV 00010001 3 RVM: trying to launch SWE 0x000A0002
[02:38:25] RV 00010001 5 RVM: SWE memory bank allocation success
[02:38:25] RV 000A0002 3 RTC : rtc_set_info: try to init GLOBAL INFO RTC structure ... 
[02:38:25] RV 00010001 5 RVM: SWE set info functions called
[02:38:25] RV 00010001 5 RVM: Created task nb  0x00000005
[02:38:25] RV 00010001 5 RVM: Resumed task nb  0x00000005
[02:38:25] RV 00010001 5 RVM: Resumed SWE  0x000A0002
[02:38:25] RV 00010001 5 RVM: SWE initialization success
[02:38:25] RV 000A0002 3 RTC: Initialization
[02:38:25] RV 00010001 3 create_RVtasks: RTC (0x000a0002) started
[02:38:25] GPF sysprim id=B7 ts=0000001C SYST->TST "IS_STACK_TIME"
[02:38:25] GPF trace id=A7 ts=0000001C SYST->PCO "&0"
[02:38:25] RV 000A0004 2 ffs_init() 0
[02:38:25] RV 000A0004 2 FFS revision: 0x5056
[02:38:25] RV 000A0004 2 FFS device, driver: 0xfe, 0x0000, 64
[02:38:25] RV 000A0004 2 FFS base, blocks: 0x103a148, 7
[02:38:25] RV 000A0004 2 FFS format read, write: 0x210, 0x210
[02:38:25] GPF trace id=A7 ts=0000008F SYST->PCO tc=05 "pei_init: no trace mask in FFS"
[02:38:26] L1:  FSL: 0 L1S
[02:38:26] L1: > CPU 0 3
[02:38:26] GPF trace id=A7 ts=00000135 SYST->PCO "L1:em_l1_sem_index cleared"
[02:38:26] GPF trace id=A7 ts=00000135 SYST->PCO "DL version is FreeCalypso"
[02:38:26] GPF trace id=A7 ts=00000135 SYST->PCO "DL:em_dl_sem_index cleared"
[02:38:26] L1: TST_C 3 TCS_3.2.0_L1_6011_1 PLUS_N5x DSP:3606h DYN:0h CHECKSUM:a1cah
[02:38:26] RV 00010001 3 MEM STAT: Total memory required 0x00003D7D
[02:38:26] RV 00010001 3 MEM STAT: Total memory obtained 0x00003E90
[02:38:26] RV 00010001 3 MEM STAT: Total memory used     0x00004788
[02:38:26] RV 00010001 3 MEM STAT: Mem usage ratio      : 098.725248%
[02:38:26] RV 00010001 3 *** START DUMPING MEMORY BANK ***
[02:38:26] RV 00010001 3 **MB_NAME* Id Used_mem Watermark  Limit   Peak Nb_buff Avg_buf_size
[02:38:26] RV 00010001 3   RVM_PRIM  0      360      5900   6000    548       0           67
[02:38:26] RV 00010001 3   RV_TRACE 59      984     25000  25000   3740       0           63
[02:38:26] RV 00010001 3 RVM_STACKS  6     7248      7948   7948   7248       0         1208
[02:38:26] RV 00010001 3    RVM_SYS  7     1976      8900   9000   1976       0           93
[02:38:26] L1:  FSL: 4 2 osload 0
[02:38:26] L1: > CPU 4 5
[02:38:26] RV 00010001 3  RVM_TIMER  8        0      2500   3000      0       0            0
[02:38:26] RV 00010001 3 RVM_NOTIFY  9        0      2500   3000      0       0            0
[02:38:26] RV 00010001 3   FFS_PRIM 10       48      6216   9216     96       0           48
[02:38:26] RV 00010001 3   SPI_PRIM 11       24       200    256     24       0           24
[02:38:26] RV 00010001 3   ETM_PRIM 12        8      1024   1024     48       0           32
[02:38:26] RV 00010001 3   RTC_PRIM 13       20        80    100     20       0           10
[02:38:26] RV 00010001 3 TOTAL: ********  10764**********  64544  13700
[02:38:26] RV 00010001 3 *** START DUMPING MEMORY ***
[02:38:26] RV 00010001 3 Total memory available  0x000138AC
[02:38:26] RV 00010001 3 Memory currently in use 0x00003208
[02:38:26] RV 00010001 3 *** START DUMPING TASKS ***
[02:38:26] RV 00010001 3 *TASK_NAME Id Stack_size Used_stack
[02:38:26] RV 00010001 3        RVM  0       1500        792
[02:38:26] RV 00010001 3      TRACE  1       2000        276
[02:38:26] RV 00010001 3        FFS  2       1024        296
[02:38:26] RV 00010001 3        SPI  3       1000        224
[02:38:26] RV 00010001 3        ETM  4       1024        252
[02:38:26] RV 00010001 3        RTC  5        700        224
[02:38:26] RV 00010001 3   RV_START 29       1024        464
[02:38:26] GPF trace id=A7 ts=0000015A SYST->PCO "RR:em_rr_sem_index cleared"
[02:38:26] GPF trace id=A7 ts=0000015A SYST->PCO tc=05 "All tasks entered main loop"
[02:38:26] L1: ADC_R 28
[02:38:26] RV 000A0010 5 SPI: ADC are on
[02:38:26] L1:  FSL: 95 L1S
[02:38:46] RV 00000000 1 RVT: System Time 000010F4
[02:38:46] L1:       ADC :4283 0
[02:38:46] RV 000A0010 5 IQ EXT: ADC End
[02:38:46] L1:  FSL: 4284 2 osload 0
[02:38:47] L1:  FSL: 4379 L1S
[02:38:48] L1:  FSL: 4590 2 osload 0
[02:38:48] L1:  FSL: 4670 L1S
[02:38:48] L1:       ADC :4691 0
[02:38:48] RV 000A0010 5 IQ EXT: ADC End
[02:38:48] L1:  FSL: 4692 2 osload 0
[02:38:49] L1:  FSL: 4772 L1S
[02:38:49] L1:       ADC :4793 0
[02:38:49] RV 000A0010 5 IQ EXT: ADC End
[02:38:49] L1:  FSL: 4794 2 osload 0
[02:38:49] L1:  FSL: 4874 L1S
[02:38:49] L1:       ADC :4895 0
[02:38:49] RV 000A0010 5 IQ EXT: ADC End
[02:38:49] L1:  FSL: 4896 2 osload 0
[02:38:49] L1:  FSL: 4976 L1S
[02:38:50] L1:       ADC :4997 0
[02:38:50] RV 000A0010 5 IQ EXT: ADC End
[02:38:50] L1:  FSL: 4998 2 osload 0
[02:38:50] L1:  FSL: 5078 L1S
[02:38:50] L1:       ADC :5099 0
[02:38:50] RV 000A0010 5 IQ EXT: ADC End
[02:38:50] L1:  FSL: 5100 2 osload 0
[02:38:50] L1:  FSL: 5180 L1S
[02:38:51] L1:       ADC :5201 0
[02:38:51] RV 000A0010 5 IQ EXT: ADC End
[02:38:51] L1:  FSL: 5202 2 osload 0
[02:38:51] L1:  FSL: 5282 L1S
[02:38:51] L1:       ADC :5303 0
[02:38:51] RV 000A0010 5 IQ EXT: ADC End
[02:38:51] L1:  FSL: 5304 2 osload 0
[02:38:51] L1:  FSL: 5384 L1S
[02:38:51] L1: > CPU 5305 4
[02:38:51] L1:       ADC :5405 0
[02:38:51] RV 000A0010 5 IQ EXT: ADC End
[02:38:51] L1:  FSL: 5406 2 osload 0
[02:38:51] L1: > CPU 5406 5
[02:38:52] L1:  FSL: 5486 L1S
[02:38:52] L1:       ADC :5507 0
[02:38:52] RV 000A0010 5 IQ EXT: ADC End
[02:38:52] L1:  FSL: 5508 2 osload 0
[02:38:52] L1:  FSL: 5588 L1S
[02:38:52] L1:       ADC :5609 0
[02:38:52] RV 000A0010 5 IQ EXT: ADC End
[02:38:52] L1:  FSL: 5610 2 osload 0
[02:38:53] L1:  FSL: 5690 L1S
[02:38:53] L1:       ADC :5711 0
[02:38:53] RV 000A0010 5 IQ EXT: ADC End
[02:38:53] L1:  FSL: 5712 2 osload 0
[02:38:53] L1:  FSL: 5792 L1S
[02:38:53] L1:       ADC :5813 0
[02:38:53] RV 000A0010 5 IQ EXT: ADC End
[02:38:53] L1:  FSL: 5814 2 osload 0
[02:38:54] L1:  FSL: 5894 L1S
[02:38:54] L1:       ADC :5915 0
[02:38:54] RV 000A0010 5 IQ EXT: ADC End
[02:38:54] L1:  FSL: 5916 2 osload 0
[02:38:54] L1:  FSL: 5996 L1S
[02:38:54] L1:       ADC :6017 0
[02:38:54] RV 000A0010 5 IQ EXT: ADC End
[02:38:54] L1:  FSL: 6018 2 osload 0
[02:38:55] L1:  FSL: 6098 L1S
[02:38:55] L1:       ADC :6119 0
[02:38:55] RV 000A0010 5 IQ EXT: ADC End
[02:38:55] L1:  FSL: 6120 2 osload 0
[02:38:55] L1:  FSL: 6200 L1S
[02:38:55] L1:       ADC :6221 0
[02:38:55] RV 000A0010 5 IQ EXT: ADC End
[02:38:55] L1:  FSL: 6222 2 osload 0
[02:38:56] L1:  FSL: 6302 L1S
[02:38:56] L1:       ADC :6323 0
[02:38:56] RV 000A0010 5 IQ EXT: ADC End
[02:38:56] L1:  FSL: 6324 2 osload 0
[02:38:56] L1:  FSL: 6404 L1S
[02:38:56] L1:       ADC :6425 0
[02:38:56] RV 000A0010 5 IQ EXT: ADC End
[02:38:56] L1:  FSL: 6426 2 osload 0
[02:38:57] L1:  FSL: 6506 L1S
[02:38:57] L1:       ADC :6527 0
[02:38:57] RV 000A0010 5 IQ EXT: ADC End
[02:38:57] L1:  FSL: 6528 2 osload 0
[02:38:57] L1:  FSL: 6608 L1S
[02:38:57] L1:       ADC :6629 0
[02:38:57] RV 000A0010 5 IQ EXT: ADC End
[02:38:57] L1:  FSL: 6630 2 osload 0
[02:38:57] L1:  FSL: 6710 L1S
[02:38:57] L1: > CPU 6631 4
[02:38:58] L1:       ADC :6731 0
[02:38:58] RV 000A0010 5 IQ EXT: ADC End
[02:38:58] L1:  FSL: 6732 2 osload 0
[02:38:58] L1: > CPU 6732 5
[02:38:58] L1:  FSL: 6812 L1S
[02:38:58] L1:       ADC :6833 0
[02:38:58] RV 000A0010 5 IQ EXT: ADC End
[02:38:58] L1:  FSL: 6834 2 osload 0
[02:38:58] L1:  FSL: 6914 L1S
[02:38:59] L1:       ADC :6935 0
[02:38:59] RV 000A0010 5 IQ EXT: ADC End
[02:38:59] L1:  FSL: 6936 2 osload 0
[02:38:59] L1:  FSL: 7016 L1S
[02:38:59] L1:       ADC :7037 0
[02:38:59] RV 000A0010 5 IQ EXT: ADC End
[02:38:59] L1:  FSL: 7038 2 osload 0
[02:38:59] L1:  FSL: 7118 L1S
[02:38:59] L1:       ADC :7139 0
[02:38:59] RV 000A0010 5 IQ EXT: ADC End
[02:38:59] L1:  FSL: 7140 2 osload 0
[02:39:00] L1:  FSL: 7220 L1S
[02:39:00] L1:       ADC :7241 0
[02:39:00] RV 000A0010 5 IQ EXT: ADC End
[02:39:00] L1:  FSL: 7242 2 osload 0
[02:39:00] L1:  FSL: 7322 L1S
[02:39:00] L1:       ADC :7343 0
[02:39:00] RV 000A0010 5 IQ EXT: ADC End
[02:39:00] L1:  FSL: 7344 2 osload 0
[02:39:01] L1:  FSL: 7424 L1S
[02:39:01] L1:       ADC :7445 0
[02:39:01] RV 000A0010 5 IQ EXT: ADC End
[02:39:01] L1:  FSL: 7446 2 osload 0
[02:39:01] L1:  FSL: 7526 L1S
[02:39:01] L1:       ADC :7547 0
[02:39:01] RV 000A0010 5 IQ EXT: ADC End
[02:39:01] L1:  FSL: 7548 2 osload 0
[02:39:02] L1:  FSL: 7628 L1S
[02:39:02] L1:       ADC :7649 0
[02:39:02] RV 000A0010 5 IQ EXT: ADC End
[02:39:02] L1:  FSL: 7650 2 osload 0
[02:39:02] L1:  FSL: 7730 L1S
[02:39:02] L1:       ADC :7751 0
[02:39:02] RV 000A0010 5 IQ EXT: ADC End
[02:39:02] L1:  FSL: 7752 2 osload 0
[02:39:03] L1:  FSL: 7832 L1S
[02:39:03] L1:       ADC :7853 0
[02:39:03] RV 000A0010 5 IQ EXT: ADC End
[02:39:03] L1:  FSL: 7854 2 osload 0
[02:39:03] L1:  FSL: 7934 L1S
[02:39:03] L1:       ADC :7955 0
[02:39:03] RV 000A0010 5 IQ EXT: ADC End
[02:39:03] L1:  FSL: 7956 2 osload 0
[02:39:04] L1:  FSL: 8036 L1S
[02:39:04] L1: > CPU 7957 4
[02:39:04] L1:       ADC :8057 0
[02:39:04] RV 000A0010 5 IQ EXT: ADC End
[02:39:04] L1:  FSL: 8058 2 osload 0
[02:39:04] L1: > CPU 8058 5
[02:39:04] L1:  FSL: 8138 L1S
[02:39:04] L1:       ADC :8159 0
[02:39:04] RV 000A0010 5 IQ EXT: ADC End
[02:39:04] L1:  FSL: 8160 2 osload 0
[02:39:05] L1:  FSL: 8240 L1S
[02:39:05] L1:       ADC :8261 0
[02:39:05] RV 000A0010 5 IQ EXT: ADC End
[02:39:05] L1:  FSL: 8262 2 osload 0
[02:39:05] L1:  FSL: 8342 L1S
[02:39:05] L1:       ADC :8363 0
[02:39:05] RV 000A0010 5 IQ EXT: ADC End
[02:39:05] L1:  FSL: 8364 2 osload 0
[02:39:05] L1:  FSL: 8444 L1S
[02:39:06] L1:       ADC :8465 0
[02:39:06] RV 000A0010 5 IQ EXT: ADC End
[02:39:06] L1:  FSL: 8466 2 osload 0
[02:39:06] L1:  FSL: 8546 L1S
[02:39:06] L1:       ADC :8567 0
[02:39:06] RV 000A0010 5 IQ EXT: ADC End
[02:39:06] L1:  FSL: 8568 2 osload 0
[02:39:06] RV 00000000 1 RVT: System Time 000021E2
[02:39:06] L1:  FSL: 8648 L1S
[02:39:07] L1:       ADC :8669 0
[02:39:07] RV 000A0010 5 IQ EXT: ADC End
[02:39:07] L1:  FSL: 8670 2 osload 0
[02:39:07] L1:  FSL: 8750 L1S
[02:39:07] L1:       ADC :8771 0
[02:39:07] RV 000A0010 5 IQ EXT: ADC End
[02:39:07] L1:  FSL: 8772 2 osload 0
[02:39:07] L1:  FSL: 8852 L1S
[02:39:07] L1:       ADC :8873 0
[02:39:07] RV 000A0010 5 IQ EXT: ADC End
[02:39:07] L1:  FSL: 8874 2 osload 0
[02:39:08] L1:  FSL: 8954 L1S
[02:39:08] L1:       ADC :8975 0
[02:39:08] RV 000A0010 5 IQ EXT: ADC End
[02:39:08] L1:  FSL: 8976 2 osload 0
[02:39:08] L1:  FSL: 9056 L1S
[02:39:08] L1:       ADC :9077 0
[02:39:08] RV 000A0010 5 IQ EXT: ADC End
[02:39:08] L1:  FSL: 9078 2 osload 0
[02:39:09] L1:  FSL: 9158 L1S
[02:39:09] L1:       ADC :9179 0
[02:39:09] RV 000A0010 5 IQ EXT: ADC End
[02:39:09] L1:  FSL: 9180 2 osload 0
[02:39:09] L1:  FSL: 9260 L1S
[02:39:09] L1:       ADC :9281 0
[02:39:09] RV 000A0010 5 IQ EXT: ADC End
[02:39:09] L1:  FSL: 9282 2 osload 0
[02:39:10] L1:  FSL: 9362 L1S
[02:39:10] L1: > CPU 9283 4
[02:39:10] L1:       ADC :9383 0
[02:39:10] RV 000A0010 5 IQ EXT: ADC End
[02:39:10] L1:  FSL: 9384 2 osload 0
[02:39:10] L1: > CPU 9384 5
[02:39:10] L1:  FSL: 9464 L1S
[02:39:10] L1:       ADC :9485 0
[02:39:10] RV 000A0010 5 IQ EXT: ADC End
[02:39:10] L1:  FSL: 9486 2 osload 0
[02:39:10] L1: BAND_R 6
[02:39:10] L1: BAND_C
[02:39:10] L1: RXL_R 9525 61640
[02:39:10] L1:       ADC :9526 0
[02:39:10] L1: > CPU 9526 9
[02:39:10] L1:  FSL: 9526 L1S
[02:39:11] RV 000A0010 5 IQ EXT: ADC End
[02:39:11] L1: > CPU 9528 13
[02:39:11] L1: RXL_I 9596 513 1
[02:39:11] L1: RXL_I 9596 513 1
[02:39:11] L1: BAND_R 8
[02:39:11] L1: BAND_C
[02:39:11] L1:  FSL: 9597 2 osload 0
[02:39:11] L1: RXL_R 9612 61640
[02:39:11] L1:       ADC :9613 0
[02:39:11] L1:  FSL: 9613 L1S
[02:39:11] RV 000A0010 5 IQ EXT: ADC End
[02:39:11] L1: RXL_I 9683 513 2
[02:39:11] L1: RXL_I 9683 513 2
[02:39:11] L1: BAND_R 6
[02:39:11] L1: BAND_C
[02:39:11] L1:       ADC :9689 0
[02:39:11] RV 000A0010 5 IQ EXT: ADC End
[02:39:11] L1:  FSL: 9690 2 osload 0
[02:39:11] L1: RXL_R 9699 61640
[02:39:11] L1:       ADC :9700 0
[02:39:11] L1:  FSL: 9700 L1S
[02:39:11] RV 000A0010 5 IQ EXT: ADC End
[02:39:12] L1: Warning : IQ LOW 9757 200
[02:39:12] L1: > CPU 9757 15
[02:39:12] L1: >  PM 9757 200 0 9758 9757 0 0 43528 200
[02:39:12] L1: 01000000000000000000000000000000^J
[02:39:12] L1: 
[02:39:12] L1: SW version: TCS.3.2.0_L1_6011_1
[02:39:12] L1: 
[02:39:12] +  array index: 22
[02:39:12] L1: 22: 106
[02:39:12] L1: 23: 106
[02:39:12] L1: 24: 106
[02:39:12] L1: 25: 106
[02:39:12] L1: 26: 120
[02:39:12] L1: 27: 106
[02:39:12] L1: 28: 106
[02:39:12] L1: 29: 106
[02:39:12] L1: 30: 106
[02:39:12] L1: 31: 106
[02:39:12] L1: 32: 106
[02:39:12] L1: 33: 106
[02:39:12] L1: 34: 106
[02:39:12] L1: 35: 117
[02:39:12] L1: 36: 106
[02:39:12] L1: 37: 106
[02:39:12] L1: 38: 106
[02:39:12] L1: 39: 106
[02:39:12] L1: 0: 106
[02:39:12] L1: 1: 106
[02:39:12] L1: 2: 106
[02:39:12] L1: 3: 106
[02:39:12] L1: 4: 120
[02:39:12] L1: 5: 106
[02:39:12] L1: 6: 106
[02:39:12] L1: 7: 106
[02:39:12] L1: 8: 106
[02:39:12] L1: 9: 106
[02:39:12] L1: 10: 106
[02:39:12] L1: 11: 106
[02:39:12] L1: 12: 106
[02:39:12] L1: 13: 117
[02:39:12] L1: 14: 106
[02:39:12] L1: 15: 106
[02:39:12] L1: 16: 106
[02:39:12] L1: 17: 106
[02:39:12] L1: 18: 106
[02:39:12] L1: 19: 106
[02:39:12] L1: 20: 106
[02:39:12] L1: 21: 106
[02:39:12] L1: > !PM 9758 200 0 9759 9758 0 0 43528
[02:39:12] L1: RXL_I 9770 513 3
[02:39:12] L1: RXL_I 9770 513 3
[02:39:12] L1: BAND_R 8
[02:39:12] L1: BAND_C
[02:39:12] L1: RXL_R 9786 61640
[02:39:12] L1:       ADC :9787 0
[02:39:12] RV 000A0010 5 IQ EXT: ADC End
[02:39:12] L1: Warning : IQ LOW 9822 200
[02:39:12] L1: >  PM 9822 200 0 9823 9822 0 0 43528 200
[02:39:12] L1: > !PM 9823 200 0 9824 9823 0 0 43528
[02:39:12] L1: Warning : IQ LOW 9829 200
[02:39:12] L1: >  PM 9829 200 0 9830 9829 0 0 43528 200
[02:39:12] L1: > !PM 9830 200 0 9831 9830 0 0 43528
[02:39:12] L1: RXL_I 9857 513 4
[02:39:12] L1: RXL_I 9857 513 4
[02:39:12] L1: BAND_R 6
[02:39:12] L1: BAND_C
[02:39:12] L1:  FSL: 9858 2 osload 0
[02:39:12] L1:  FSL: 9872 L1S
[02:39:12] L1: RXL_R 9873 61640
[02:39:12] L1:       ADC :9874 0
[02:39:12] RV 000A0010 5 IQ EXT: ADC End
[02:39:12] L1: RXL_I 9944 513 5
[02:39:12] L1: RXL_I 9944 513 5
[02:39:12] + (1024 519)(1288 774)(65287 770)(0 256)(257 257)(256 256)(257 256)(41288 259)(12200 256)(16682 19794)
[02:39:12] L1: BAND_R 8
[02:39:12] L1: BAND_C
[02:39:12] L1:  FSL: 9945 2 osload 0
[02:39:12] L1: RXL_R 9960 61640
[02:39:13] L1:       ADC :9961 0
[02:39:13] L1:  FSL: 9961 L1S
[02:39:13] RV 000A0010 5 IQ EXT: ADC End
[02:39:13] L1: RXL_I 10031 513 1
[02:39:13] L1: RXL_I 10031 513 1
[02:39:13] L1: BAND_R 6
[02:39:13] L1: BAND_C
[02:39:13] L1:  FSL: 10032 2 osload 0
[02:39:13] L1: RXL_R 10047 61640
[02:39:13] L1:       ADC :10048 0
[02:39:13] L1:  FSL: 10048 L1S
[02:39:13] RV 000A0010 5 IQ EXT: ADC End
[02:39:13] L1: Warning : IQ LOW 10076 200
[02:39:13] L1: >  PM 10076 200 0 10077 10076 0 0 43528 200
[02:39:13] L1: > !PM 10077 200 0 10078 10077 0 0 43528
[02:39:13] L1: RXL_I 10118 513 2
[02:39:13] L1: RXL_I 10118 513 2
[02:39:13] L1: BAND_R 8
[02:39:13] L1: BAND_C
[02:39:13] L1:  FSL: 10119 2 osload 0
[02:39:13] L1: RXL_R 10134 61640
[02:39:13] L1:       ADC :10135 0
[02:39:13] L1:  FSL: 10135 L1S
[02:39:13] RV 000A0010 5 IQ EXT: ADC End
[02:39:13] L1: Warning : IQ LOW 10142 200
[02:39:13] L1: >  PM 10142 200 0 10143 10142 0 0 43528 200
[02:39:13] L1: > !PM 10143 200 0 10144 10143 0 0 43528
[02:39:14] L1: Warning : IQ LOW 10178 200
[02:39:14] L1: >  PM 10178 200 0 10179 10178 0 0 43528 200
[02:39:14] L1: > !PM 10179 200 0 10180 10179 0 0 43528
[02:39:14] L1: RXL_I 10205 513 3
[02:39:14] L1: RXL_I 10205 513 3
[02:39:14] L1: BAND_R 6
[02:39:14] L1: BAND_C
[02:39:14] L1:  FSL: 10206 2 osload 0
[02:39:14] L1: RXL_R 10221 61640
[02:39:14] L1:       ADC :10222 0
[02:39:14] L1:  FSL: 10222 L1S
[02:39:14] RV 000A0010 5 IQ EXT: ADC End
[02:39:14] L1: Warning : IQ LOW 10244 200
[02:39:14] L1: >  PM 10244 200 0 10245 10244 0 0 43528 200
[02:39:14] L1: > !PM 10245 200 0 10246 10245 0 0 43528
[02:39:14] L1: Warning : IQ LOW 10246 200
[02:39:14] L1: >  PM 10246 200 0 10247 10246 0 0 43528 200
[02:39:14] L1: > !PM 10247 200 0 10248 10247 0 0 43528
[02:39:14] L1: Warning : IQ LOW 10251 200
[02:39:14] L1: >  PM 10251 200 0 10252 10251 0 0 43528 200
[02:39:14] L1: > !PM 10252 200 0 10253 10252 0 0 43528
[02:39:14] L1: Warning : IQ LOW 10253 200
[02:39:14] L1: >  PM 10253 200 0 10254 10253 0 0 43528 200
[02:39:14] L1: > !PM 10254 200 0 10255 10254 0 0 43528
[02:39:14] GPF trace id=A7 ts=0000BAA8 PL->PCO tc=07 "HM cb_mmi_sat_cbch_req(), sat_enabled = 1, modus = 255"
[02:39:14] GPF trace id=A7 ts=0000BAA8 SYST->PCO tc=07 "TRACE ERROR in PL"
[02:39:14] L1: RXL_I 10292 513 4
[02:39:14] L1: RXL_I 10292 513 4
[02:39:14] L1: BAND_R 8
[02:39:14] L1: BAND_C
[02:39:14] L1:       ADC :10301 0
[02:39:14] RV 000A0010 5 IQ EXT: ADC End
[02:39:14] L1:  FSL: 10302 2 osload 0
[02:39:14] L1: RXL_R 10308 61640
[02:39:14] L1:       ADC :10309 0
[02:39:14] L1:  FSL: 10309 L1S
[02:39:14] RV 000A0010 5 IQ EXT: ADC End
[02:39:14] L1: Warning : IQ LOW 10354 200
[02:39:14] L1: >  PM 10354 200 0 10355 10354 0 0 43528 200
[02:39:14] L1: > !PM 10355 200 0 10356 10355 0 0 43528
[02:39:14] L1: Warning : IQ LOW 10361 200
[02:39:14] L1: >  PM 10361 200 0 10362 10361 0 0 43528 200
[02:39:14] L1: > !PM 10362 200 0 10363 10362 0 0 43528
[02:39:14] L1: RXL_I 10379 513 5
[02:39:14] L1: RXL_I 10379 513 5
[02:39:14] + (1024 519)(1288 774)(65287 770)(0 256)(257 257)(256 256)(257 256)(41288 259)(12200 256)(16682 19794)
[02:39:14] L1:  FSL: 10380 2 osload 0
[02:39:14] L1:  FSL: 10382 L1S
[02:39:15] L1:       ADC :10403 0
[02:39:15] RV 000A0010 5 IQ EXT: ADC End
[02:39:15] L1:  FSL: 10404 2 osload 0
[02:39:15] L1:  FSL: 10484 L1S
[02:39:15] L1:       ADC :10505 0
[02:39:15] RV 000A0010 5 IQ EXT: ADC End
[02:39:15] L1:  FSL: 10506 2 osload 0
[02:39:15] L1:  FSL: 10586 L1S
[02:39:15] L1:       ADC :10607 0
[02:39:15] RV 000A0010 5 IQ EXT: ADC End
[02:39:15] L1:  FSL: 10608 2 osload 0
[02:39:16] L1:  FSL: 10688 L1S
[02:39:16] L1: > CPU 10609 3
[02:39:16] L1:       ADC :10709 0
[02:39:16] L1: > CPU 10709 4
[02:39:16] RV 000A0010 5 IQ EXT: ADC End
[02:39:16] L1:  FSL: 10710 2 osload 0
[02:39:16] L1:  FSL: 10790 L1S
[02:39:16] L1:       ADC :10811 0
[02:39:16] RV 000A0010 5 IQ EXT: ADC End
[02:39:16] L1:  FSL: 10812 2 osload 0
[02:39:17] L1:  FSL: 10892 L1S
[02:39:17] L1:       ADC :10913 0
[02:39:17] RV 000A0010 5 IQ EXT: ADC End
[02:39:17] L1:  FSL: 10914 2 osload 0
[02:39:17] L1:  FSL: 10994 L1S
[02:39:17] L1:       ADC :11015 0
[02:39:17] RV 000A0010 5 IQ EXT: ADC End
[02:39:17] L1:  FSL: 11016 2 osload 0
[02:39:18] L1:  FSL: 11096 L1S
[02:39:18] L1:       ADC :11117 0
[02:39:18] RV 000A0010 5 IQ EXT: ADC End
[02:39:18] L1:  FSL: 11118 2 osload 0
[02:39:18] L1:  FSL: 11198 L1S
[02:39:18] L1:       ADC :11219 0
[02:39:18] RV 000A0010 5 IQ EXT: ADC End
[02:39:18] L1:  FSL: 11220 2 osload 0
[02:39:19] L1:  FSL: 11300 L1S
[02:39:19] L1:       ADC :11321 0
[02:39:19] RV 000A0010 5 IQ EXT: ADC End
[02:39:19] L1:  FSL: 11322 2 osload 0
[02:39:19] L1:  FSL: 11402 L1S
[02:39:19] L1:       ADC :11423 0
[02:39:19] RV 000A0010 5 IQ EXT: ADC End
[02:39:19] L1:  FSL: 11424 2 osload 0
[02:39:20] L1:  FSL: 11504 L1S
[02:39:20] L1:       ADC :11525 0
[02:39:20] RV 000A0010 5 IQ EXT: ADC End
[02:39:20] L1:  FSL: 11526 2 osload 0
[02:39:20] L1:  FSL: 11606 L1S
[02:39:20] L1:       ADC :11627 0
[02:39:20] RV 000A0010 5 IQ EXT: ADC End
[02:39:20] L1:  FSL: 11628 2 osload 0
[02:39:21] L1:  FSL: 11708 L1S
[02:39:21] L1:       ADC :11729 0
[02:39:21] RV 000A0010 5 IQ EXT: ADC End
[02:39:21] L1:  FSL: 11730 2 osload 0
[02:39:21] L1:  FSL: 11810 L1S
[02:39:21] L1:       ADC :11831 0
[02:39:21] RV 000A0010 5 IQ EXT: ADC End
[02:39:21] L1:  FSL: 11832 2 osload 0
[02:39:22] L1:  FSL: 11912 L1S
[02:39:22] L1:       ADC :11933 0
[02:39:22] RV 000A0010 5 IQ EXT: ADC End
[02:39:22] L1:  FSL: 11934 2 osload 0
[02:39:22] L1:  FSL: 12014 L1S
[02:39:22] L1: > CPU 11935 3
[02:39:22] L1:       ADC :12035 0
[02:39:22] L1: > CPU 12035 4
[02:39:22] RV 000A0010 5 IQ EXT: ADC End
[02:39:22] L1:  FSL: 12036 2 osload 0
[02:39:22] L1:  FSL: 12116 L1S
[02:39:23] L1:       ADC :12137 0
[02:39:23] RV 000A0010 5 IQ EXT: ADC End
[02:39:23] L1:  FSL: 12138 2 osload 0
[02:39:23] L1:  FSL: 12218 L1S
[02:39:23] L1:       ADC :12239 0
[02:39:23] RV 000A0010 5 IQ EXT: ADC End
[02:39:23] L1:  FSL: 12240 2 osload 0
[02:39:23] L1:  FSL: 12320 L1S
[02:39:23] L1:       ADC :12341 0
[02:39:23] RV 000A0010 5 IQ EXT: ADC End
[02:39:23] L1:  FSL: 12342 2 osload 0
[02:39:24] L1:  FSL: 12422 L1S
[02:39:24] L1:       ADC :12443 0
[02:39:24] RV 000A0010 5 IQ EXT: ADC End
[02:39:24] L1:  FSL: 12444 2 osload 0
[02:39:24] L1:  FSL: 12524 L1S
[02:39:24] L1:       ADC :12545 0
[02:39:24] RV 000A0010 5 IQ EXT: ADC End
[02:39:24] L1:  FSL: 12546 2 osload 0
[02:39:25] L1:  FSL: 12626 L1S
[02:39:25] L1:       ADC :12647 0
[02:39:25] RV 000A0010 5 IQ EXT: ADC End
[02:39:25] L1:  FSL: 12648 2 osload 0
[02:39:25] L1:  FSL: 12728 L1S
[02:39:25] L1:       ADC :12749 0
[02:39:25] RV 000A0010 5 IQ EXT: ADC End
[02:39:25] L1:  FSL: 12750 2 osload 0
[02:39:26] L1:  FSL: 12830 L1S
[02:39:26] L1:       ADC :12851 0
[02:39:26] RV 000A0010 5 IQ EXT: ADC End
[02:39:26] L1:  FSL: 12852 2 osload 0
[02:39:26] L1: > CPU 12852 5
[02:39:26] L1:  FSL: 12932 L1S
[02:39:26] RV 00000000 1 RVT: System Time 000032D0
[02:39:26] L1:       ADC :12953 0
[02:39:26] RV 000A0010 5 IQ EXT: ADC End
[02:39:26] L1:  FSL: 12954 2 osload 0
[02:39:27] L1:  FSL: 13034 L1S
[02:39:27] L1:       ADC :13055 0
[02:39:27] RV 000A0010 5 IQ EXT: ADC End
[02:39:27] L1:  FSL: 13056 2 osload 0
[02:39:27] L1:  FSL: 13136 L1S
[02:39:27] L1:       ADC :13157 0
[02:39:27] RV 000A0010 5 IQ EXT: ADC End
[02:39:27] L1:  FSL: 13158 2 osload 0
[02:39:28] L1:  FSL: 13238 L1S
[02:39:28] L1:       ADC :13259 0
[02:39:28] RV 000A0010 5 IQ EXT: ADC End
[02:39:28] L1:  FSL: 13260 2 osload 0
[02:39:28] L1:  FSL: 13340 L1S
[02:39:28] L1: > CPU 13261 3
[02:39:28] L1:       ADC :13361 0
[02:39:28] L1: > CPU 13361 4
[02:39:28] RV 000A0010 5 IQ EXT: ADC End
[02:39:28] L1:  FSL: 13362 2 osload 0
[02:39:29] L1:  FSL: 13442 L1S
[02:39:29] L1:       ADC :13463 0
[02:39:29] RV 000A0010 5 IQ EXT: ADC End
[02:39:29] L1:  FSL: 13464 2 osload 0
[02:39:29] L1:  FSL: 13544 L1S
[02:39:29] L1:       ADC :13565 0
[02:39:29] RV 000A0010 5 IQ EXT: ADC End
[02:39:29] L1:  FSL: 13566 2 osload 0
[02:39:30] L1:  FSL: 13646 L1S
[02:39:30] L1:       ADC :13667 0
[02:39:30] RV 000A0010 5 IQ EXT: ADC End
[02:39:30] L1:  FSL: 13668 2 osload 0
[02:39:30] L1:  FSL: 13748 L1S
[02:39:30] L1:       ADC :13769 0
[02:39:30] RV 000A0010 5 IQ EXT: ADC End
[02:39:30] L1:  FSL: 13770 2 osload 0
[02:39:30] L1:  FSL: 13850 L1S
[02:39:31] L1:       ADC :13871 0
[02:39:31] RV 000A0010 5 IQ EXT: ADC End
[02:39:31] L1:  FSL: 13872 2 osload 0
[02:39:31] L1:  FSL: 13952 L1S
[02:39:31] L1:       ADC :13973 0
[02:39:31] RV 000A0010 5 IQ EXT: ADC End
[02:39:31] L1:  FSL: 13974 2 osload 0
[02:39:31] L1:  FSL: 14054 L1S
[02:39:31] L1:       ADC :14075 0
[02:39:31] RV 000A0010 5 IQ EXT: ADC End
[02:39:31] L1:  FSL: 14076 2 osload 0
[02:39:32] L1:  FSL: 14156 L1S
[02:39:32] L1:       ADC :14177 0
[02:39:32] RV 000A0010 5 IQ EXT: ADC End
[02:39:32] L1:  FSL: 14178 2 osload 0
[02:39:32] L1:  FSL: 14258 L1S
[02:39:32] L1:       ADC :14279 0
[02:39:32] RV 000A0010 5 IQ EXT: ADC End
[02:39:32] L1:  FSL: 14280 2 osload 0
[02:39:33] L1:  FSL: 14360 L1S
[02:39:33] L1:       ADC :14381 0
[02:39:33] RV 000A0010 5 IQ EXT: ADC End
[02:39:33] L1:  FSL: 14382 2 osload 0
[02:39:33] L1:  FSL: 14462 L1S
[02:39:33] L1:       ADC :14483 0
[02:39:33] RV 000A0010 5 IQ EXT: ADC End
[02:39:33] L1:  FSL: 14484 2 osload 0
[02:39:34] L1:  FSL: 14564 L1S
[02:39:34] L1:       ADC :14585 0
[02:39:34] RV 000A0010 5 IQ EXT: ADC End
[02:39:34] L1:  FSL: 14586 2 osload 0
[02:39:34] L1:  FSL: 14666 L1S
[02:39:34] L1: > CPU 14587 3
[02:39:34] L1:       ADC :14687 0
[02:39:34] L1: > CPU 14687 4
[02:39:34] RV 000A0010 5 IQ EXT: ADC End
[02:39:34] L1:  FSL: 14688 2 osload 0
[02:39:35] L1:  FSL: 14768 L1S
[02:39:35] L1:       ADC :14789 0
[02:39:35] RV 000A0010 5 IQ EXT: ADC End
[02:39:35] L1:  FSL: 14790 2 osload 0
[02:39:35] L1:  FSL: 14870 L1S
[02:39:35] L1:       ADC :14891 0
[02:39:35] RV 000A0010 5 IQ EXT: ADC End
[02:39:35] L1:  FSL: 14892 2 osload 0
[02:39:36] L1:  FSL: 14972 L1S
[02:39:36] L1:       ADC :14993 0
[02:39:36] RV 000A0010 5 IQ EXT: ADC End
[02:39:36] L1:  FSL: 14994 2 osload 0
[02:39:36] L1:  FSL: 15074 L1S
[02:39:36] L1:       ADC :15095 0
[02:39:36] RV 000A0010 5 IQ EXT: ADC End
[02:39:36] L1:  FSL: 15096 2 osload 0
[02:39:37] L1:  FSL: 15176 L1S
[02:39:37] L1:       ADC :15197 0
[02:39:37] RV 000A0010 5 IQ EXT: ADC End
[02:39:37] L1:  FSL: 15198 2 osload 0
[02:39:37] L1:  FSL: 15278 L1S
[02:39:37] L1:       ADC :15299 0
[02:39:37] RV 000A0010 5 IQ EXT: ADC End
[02:39:37] L1:  FSL: 15300 2 osload 0
[02:39:38] L1:  FSL: 15380 L1S
[02:39:38] L1:       ADC :15401 0
[02:39:38] RV 000A0010 5 IQ EXT: ADC End
[02:39:38] L1:  FSL: 15402 2 osload 0
[02:39:38] L1:  FSL: 15482 L1S
[02:39:38] L1:       ADC :15503 0
[02:39:38] RV 000A0010 5 IQ EXT: ADC End
[02:39:38] L1:  FSL: 15504 2 osload 0
[02:39:38] L1:  FSL: 15584 L1S
[02:39:39] L1:       ADC :15605 0
[02:39:39] RV 000A0010 5 IQ EXT: ADC End
[02:39:39] L1:  FSL: 15606 2 osload 0
[02:39:39] L1:  FSL: 15686 L1S
[02:39:39] L1:       ADC :15707 0
[02:39:39] RV 000A0010 5 IQ EXT: ADC End
[02:39:39] L1:  FSL: 15708 2 osload 0
[02:39:39] L1:  FSL: 15788 L1S
[02:39:39] L1:       ADC :15809 0
[02:39:39] RV 000A0010 5 IQ EXT: ADC End
[02:39:39] L1:  FSL: 15810 2 osload 0
[02:39:40] L1:  FSL: 15890 L1S
[02:39:40] L1:       ADC :15911 0
[02:39:40] RV 000A0010 5 IQ EXT: ADC End
[02:39:40] L1:  FSL: 15912 2 osload 0
[02:39:40] L1:  FSL: 15992 L1S
[02:39:40] L1: > CPU 15913 3
[02:39:40] L1:       ADC :16013 0
[02:39:40] L1: > CPU 16013 4
[02:39:40] RV 000A0010 5 IQ EXT: ADC End
[02:39:40] L1:  FSL: 16014 2 osload 0
[02:39:41] L1:  FSL: 16094 L1S
[02:39:41] L1:       ADC :16115 0
[02:39:41] RV 000A0010 5 IQ EXT: ADC End
[02:39:41] L1:  FSL: 16116 2 osload 0
[02:39:41] L1:  FSL: 16196 L1S
[02:39:41] L1:       ADC :16217 0
[02:39:41] RV 000A0010 5 IQ EXT: ADC End
[02:39:41] L1:  FSL: 16218 2 osload 0
[02:39:42] L1:  FSL: 16298 L1S
[02:39:42] L1:       ADC :16319 0
[02:39:42] RV 000A0010 5 IQ EXT: ADC End
[02:39:42] L1:  FSL: 16320 2 osload 0
[02:39:42] L1:  FSL: 16400 L1S
[02:39:42] L1:       ADC :16421 0
[02:39:42] RV 000A0010 5 IQ EXT: ADC End
[02:39:42] L1:  FSL: 16422 2 osload 0
[02:39:43] L1:  FSL: 16502 L1S
[02:39:43] L1:       ADC :16523 0
[02:39:43] RV 000A0010 5 IQ EXT: ADC End
[02:39:43] L1:  FSL: 16524 2 osload 0
[02:39:43] L1:  FSL: 16604 L1S
[02:39:43] L1:       ADC :16625 0
[02:39:43] RV 000A0010 5 IQ EXT: ADC End
[02:39:43] L1:  FSL: 16626 2 osload 0
[02:39:44] L1:  FSL: 16706 L1S
[02:39:44] L1:       ADC :16727 0
[02:39:44] RV 000A0010 5 IQ EXT: ADC End
[02:39:44] L1:  FSL: 16728 2 osload 0
[02:39:44] L1:  FSL: 16808 L1S
[02:39:44] L1:       ADC :16829 0
[02:39:44] RV 000A0010 5 IQ EXT: ADC End
[02:39:44] L1:  FSL: 16830 2 osload 0
[02:39:45] L1:  FSL: 16910 L1S
[02:39:45] L1:       ADC :16931 0
[02:39:45] RV 000A0010 5 IQ EXT: ADC End
[02:39:45] L1:  FSL: 16932 2 osload 0
[02:39:45] L1:  FSL: 17012 L1S
[02:39:45] L1:       ADC :17033 0
[02:39:45] RV 000A0010 5 IQ EXT: ADC End
[02:39:45] L1:  FSL: 17034 2 osload 0
[02:39:46] L1:  FSL: 17114 L1S
[02:39:46] L1:       ADC :17135 0
[02:39:46] RV 000A0010 5 IQ EXT: ADC End
[02:39:46] L1:  FSL: 17136 2 osload 0
[02:39:46] L1:  FSL: 17216 L1S
[02:39:46] L1:       ADC :17237 0
[02:39:46] RV 000A0010 5 IQ EXT: ADC End
[02:39:46] L1:  FSL: 17238 2 osload 0
[02:39:46] RV 00000000 1 RVT: System Time 000043BE
[02:39:46] L1:  FSL: 17318 L1S
[02:39:46] L1: > CPU 17239 3
[02:39:47] L1:       ADC :17339 0
[02:39:47] L1: > CPU 17339 4
[02:39:47] RV 000A0010 5 IQ EXT: ADC End
[02:39:47] L1:  FSL: 17340 2 osload 0
[02:39:47] L1:  FSL: 17420 L1S
[02:39:47] L1:       ADC :17441 0
[02:39:47] RV 000A0010 5 IQ EXT: ADC End
[02:39:47] L1:  FSL: 17442 2 osload 0
[02:39:47] L1:  FSL: 17522 L1S
[02:39:47] L1:       ADC :17543 0
[02:39:47] RV 000A0010 5 IQ EXT: ADC End
[02:39:47] L1:  FSL: 17544 2 osload 0
[02:39:48] L1:  FSL: 17624 L1S
[02:39:48] L1:       ADC :17645 0
[02:39:48] RV 000A0010 5 IQ EXT: ADC End
[02:39:48] L1:  FSL: 17646 2 osload 0
[02:39:48] L1:  FSL: 17726 L1S
[02:39:48] L1:       ADC :17747 0
[02:39:48] RV 000A0010 5 IQ EXT: ADC End
[02:39:48] L1:  FSL: 17748 2 osload 0
[02:39:49] L1:  FSL: 17828 L1S
[02:39:49] L1:       ADC :17849 0
[02:39:49] RV 000A0010 5 IQ EXT: ADC End
[02:39:49] L1:  FSL: 17850 2 osload 0
[02:39:49] L1:  FSL: 17930 L1S
[02:39:49] L1:       ADC :17951 0
[02:39:49] RV 000A0010 5 IQ EXT: ADC End
[02:39:49] L1:  FSL: 17952 2 osload 0
[02:39:50] L1:  FSL: 18032 L1S
[02:39:50] L1:       ADC :18053 0
[02:39:50] RV 000A0010 5 IQ EXT: ADC End
[02:39:50] L1:  FSL: 18054 2 osload 0
[02:39:50] L1:  FSL: 18134 L1S
[02:39:50] L1:       ADC :18155 0
[02:39:50] RV 000A0010 5 IQ EXT: ADC End
[02:39:50] L1:  FSL: 18156 2 osload 0
[02:39:51] L1:  FSL: 18236 L1S
[02:39:51] L1:       ADC :18257 0
[02:39:51] RV 000A0010 5 IQ EXT: ADC End
[02:39:51] L1:  FSL: 18258 2 osload 0
[02:39:51] L1:  FSL: 18338 L1S
[02:39:51] L1:       ADC :18359 0
[02:39:51] RV 000A0010 5 IQ EXT: ADC End
[02:39:51] L1:  FSL: 18360 2 osload 0
[02:39:52] L1:  FSL: 18440 L1S
[02:39:52] L1:       ADC :18461 0
[02:39:52] RV 000A0010 5 IQ EXT: ADC End
[02:39:52] L1:  FSL: 18462 2 osload 0
[02:39:52] L1:  FSL: 18542 L1S
[02:39:52] L1:       ADC :18563 0
[02:39:52] RV 000A0010 5 IQ EXT: ADC End
[02:39:52] L1:  FSL: 18564 2 osload 0
[02:39:53] L1:  FSL: 18644 L1S
[02:39:53] L1: > CPU 18565 3
[02:39:53] L1:       ADC :18665 0
[02:39:53] L1: > CPU 18665 4
[02:39:53] RV 000A0010 5 IQ EXT: ADC End
[02:39:53] L1:  FSL: 18666 2 osload 0
[02:39:53] L1:  FSL: 18746 L1S
[02:39:53] L1:       ADC :18767 0
[02:39:53] RV 000A0010 5 IQ EXT: ADC End
[02:39:53] L1:  FSL: 18768 2 osload 0
[02:39:54] L1:  FSL: 18848 L1S
[02:39:54] L1:       ADC :18869 0
[02:39:54] RV 000A0010 5 IQ EXT: ADC End
[02:39:54] L1:  FSL: 18870 2 osload 0
[02:39:54] L1:  FSL: 18950 L1S
[02:39:54] L1:       ADC :18971 0
[02:39:54] RV 000A0010 5 IQ EXT: ADC End
[02:39:54] L1:  FSL: 18972 2 osload 0
[02:39:54] L1:  FSL: 19052 L1S
[02:39:55] L1:       ADC :19073 0
[02:39:55] RV 000A0010 5 IQ EXT: ADC End
[02:39:55] L1:  FSL: 19074 2 osload 0
[02:39:55] L1:  FSL: 19154 L1S
[02:39:55] L1:       ADC :19175 0
[02:39:55] RV 000A0010 5 IQ EXT: ADC End
[02:39:55] L1:  FSL: 19176 2 osload 0
[02:39:55] L1:  FSL: 19256 L1S
[02:39:55] L1:       ADC :19277 0
[02:39:55] RV 000A0010 5 IQ EXT: ADC End
[02:39:56] L1:  FSL: 19278 2 osload 0
[02:39:56] L1:  FSL: 19358 L1S
[02:39:56] L1:       ADC :19379 0
[02:39:56] RV 000A0010 5 IQ EXT: ADC End
[02:39:56] L1:  FSL: 19380 2 osload 0
[02:39:56] L1:  FSL: 19460 L1S
[02:39:56] L1:       ADC :19481 0
[02:39:56] RV 000A0010 5 IQ EXT: ADC End
[02:39:56] L1:  FSL: 19482 2 osload 0
[02:39:57] L1:  FSL: 19562 L1S
[02:39:57] L1:       ADC :19583 0
[02:39:57] RV 000A0010 5 IQ EXT: ADC End
[02:39:57] L1:  FSL: 19584 2 osload 0
[02:39:57] L1:  FSL: 19664 L1S
[02:39:57] L1:       ADC :19685 0
[02:39:57] RV 000A0010 5 IQ EXT: ADC End
[02:39:57] L1:  FSL: 19686 2 osload 0
[02:39:58] L1:  FSL: 19766 L1S
[02:39:58] L1:       ADC :19787 0
[02:39:58] RV 000A0010 5 IQ EXT: ADC End
[02:39:58] L1:  FSL: 19788 2 osload 0
[02:39:58] L1:  FSL: 19868 L1S
[02:39:58] L1:       ADC :19889 0
[02:39:58] RV 000A0010 5 IQ EXT: ADC End
[02:39:58] L1:  FSL: 19890 2 osload 0
[02:39:59] L1:  FSL: 19970 L1S
[02:39:59] L1: > CPU 19891 3
[02:39:59] L1:       ADC :19991 0
[02:39:59] L1: > CPU 19991 4
[02:39:59] RV 000A0010 5 IQ EXT: ADC End
[02:39:59] L1:  FSL: 19992 2 osload 0
[02:39:59] L1:  FSL: 20072 L1S
[02:39:59] L1:       ADC :20093 0
[02:39:59] RV 000A0010 5 IQ EXT: ADC End
[02:39:59] L1:  FSL: 20094 2 osload 0
[02:40:00] L1:  FSL: 20174 L1S
[02:40:00] L1:       ADC :20195 0
[02:40:00] RV 000A0010 5 IQ EXT: ADC End
[02:40:00] L1:  FSL: 20196 2 osload 0
[02:40:00] L1:  FSL: 20276 L1S
[02:40:00] L1:       ADC :20297 0
[02:40:00] RV 000A0010 5 IQ EXT: ADC End
[02:40:00] L1:  FSL: 20298 2 osload 0
[02:40:01] L1:  FSL: 20378 L1S
[02:40:01] L1:       ADC :20399 0
[02:40:01] RV 000A0010 5 IQ EXT: ADC End
[02:40:01] L1:  FSL: 20400 2 osload 0
[02:40:01] L1:  FSL: 20480 L1S
[02:40:01] L1:       ADC :20501 0
[02:40:01] RV 000A0010 5 IQ EXT: ADC End
[02:40:01] L1:  FSL: 20502 2 osload 0
[02:40:02] L1:  FSL: 20582 L1S
[02:40:02] L1:       ADC :20603 0
[02:40:02] RV 000A0010 5 IQ EXT: ADC End
[02:40:02] L1:  FSL: 20604 2 osload 0
[02:40:02] L1:  FSL: 20684 L1S
[02:40:02] L1:       ADC :20705 0
[02:40:02] RV 000A0010 5 IQ EXT: ADC End
[02:40:02] L1:  FSL: 20706 2 osload 0
[02:40:02] L1:  FSL: 20786 L1S
[02:40:03] L1:       ADC :20807 0
[02:40:03] RV 000A0010 5 IQ EXT: ADC End
[02:40:03] L1:  FSL: 20808 2 osload 0
[02:40:03] L1:  FSL: 20888 L1S
[02:40:03] L1:       ADC :20909 0
[02:40:03] RV 000A0010 5 IQ EXT: ADC End
[02:40:03] L1:  FSL: 20910 2 osload 0
[02:40:03] L1:  FSL: 20990 L1S
[02:40:03] L1:       ADC :21011 0
[02:40:04] RV 000A0010 5 IQ EXT: ADC End
[02:40:04] L1:  FSL: 21012 2 osload 0
[02:40:04] L1:  FSL: 21092 L1S
[02:40:04] L1:       ADC :21113 0
[02:40:04] RV 000A0010 5 IQ EXT: ADC End
[02:40:04] L1:  FSL: 21114 2 osload 0
[02:40:04] L1:  FSL: 21194 L1S
[02:40:04] L1:       ADC :21215 0
[02:40:04] RV 000A0010 5 IQ EXT: ADC End
[02:40:04] L1:  FSL: 21216 2 osload 0
[02:40:05] L1:  FSL: 21296 L1S
[02:40:05] L1: > CPU 21217 3
[02:40:05] L1:       ADC :21317 0
[02:40:05] L1: > CPU 21317 4
[02:40:05] RV 000A0010 5 IQ EXT: ADC End
[02:40:05] L1:  FSL: 21318 2 osload 0
[02:40:05] L1:  FSL: 21398 L1S
[02:40:05] L1:       ADC :21419 0
[02:40:05] RV 000A0010 5 IQ EXT: ADC End
[02:40:05] L1:  FSL: 21420 2 osload 0
[02:40:06] L1:  FSL: 21500 L1S
[02:40:06] L1:       ADC :21521 0
[02:40:06] RV 000A0010 5 IQ EXT: ADC End
[02:40:06] L1:  FSL: 21522 2 osload 0
[02:40:06] L1:  FSL: 21602 L1S
[02:40:06] RV 00000000 1 RVT: System Time 000054AC
[02:40:06] L1:       ADC :21623 0
[02:40:06] RV 000A0010 5 IQ EXT: ADC End
[02:40:06] L1:  FSL: 21624 2 osload 0
[02:40:06] L1: > CPU 21624 5
[02:40:07] L1:  FSL: 21704 L1S
[02:40:07] L1:       ADC :21725 0
[02:40:07] RV 000A0010 5 IQ EXT: ADC End
[02:40:07] L1:  FSL: 21726 2 osload 0
[02:40:07] L1:  FSL: 21806 L1S
[02:40:07] L1:       ADC :21827 0
[02:40:07] RV 000A0010 5 IQ EXT: ADC End
[02:40:07] L1:  FSL: 21828 2 osload 0
[02:40:08] L1:  FSL: 21908 L1S
[02:40:08] L1:       ADC :21929 0
[02:40:08] RV 000A0010 5 IQ EXT: ADC End
[02:40:08] L1:  FSL: 21930 2 osload 0
[02:40:08] L1:  FSL: 22010 L1S
[02:40:08] L1:       ADC :22031 0
[02:40:08] RV 000A0010 5 IQ EXT: ADC End
[02:40:08] L1:  FSL: 22032 2 osload 0
[02:40:09] L1:  FSL: 22112 L1S
[02:40:09] L1:       ADC :22133 0
[02:40:09] RV 000A0010 5 IQ EXT: ADC End
[02:40:09] L1:  FSL: 22134 2 osload 0
[02:40:09] L1:  FSL: 22229 L1S
[02:40:17] L1:  FSL: 23834 2 osload 0
[02:40:17] L1:  FSL: 23846 L1S
[02:40:17] L1:       ADC :23867 0
[02:40:17] RV 000A0010 5 IQ EXT: ADC End
[02:40:17] L1:  FSL: 23868 2 osload 0
[02:40:17] L1:  FSL: 23948 L1S
[02:40:17] L1: > CPU 23869 4
[02:40:18] L1:       ADC :23969 0
[02:40:18] RV 000A0010 5 IQ EXT: ADC End
[02:40:18] L1:  FSL: 23970 2 osload 0
[02:40:18] L1: > CPU 23970 5
[02:40:18] L1:  FSL: 24050 L1S
[02:40:18] L1:       ADC :24071 0
[02:40:18] RV 000A0010 5 IQ EXT: ADC End
[02:40:18] L1:  FSL: 24072 2 osload 0
[02:40:18] L1:  FSL: 24152 L1S
[02:40:18] L1:       ADC :24173 0
[02:40:18] RV 000A0010 5 IQ EXT: ADC End
[02:40:18] L1:  FSL: 24174 2 osload 0
[02:40:19] L1: BAND_R 6
[02:40:19] L1: BAND_C
[02:40:19] L1: RXL_R 24196 61640
[02:40:19] L1:       ADC :24197 0
[02:40:19] L1: > CPU 24197 9
[02:40:19] L1:  FSL: 24197 L1S
[02:40:19] RV 000A0010 5 IQ EXT: ADC End
[02:40:19] L1: > CPU 24267 13
[02:40:19] L1: RXL_I 24267 513 1
[02:40:19] L1: RXL_I 24267 513 1
[02:40:19] L1: BAND_R 8
[02:40:19] L1: BAND_C
[02:40:19] L1:       ADC :24275 0
[02:40:19] RV 000A0010 5 IQ EXT: ADC End
[02:40:19] L1:  FSL: 24276 2 osload 0
[02:40:19] L1: RXL_R 24283 61640
[02:40:19] L1:       ADC :24284 0
[02:40:19] L1:  FSL: 24284 L1S
[02:40:19] RV 000A0010 5 IQ EXT: ADC End
[02:40:19] L1: RXL_I 24354 513 2
[02:40:19] L1: RXL_I 24354 513 2
[02:40:19] L1: BAND_R 6
[02:40:19] L1: BAND_C
[02:40:19] L1:  FSL: 24355 2 osload 0
[02:40:19] L1:  FSL: 24356 L1S
[02:40:19] L1: RXL_R 24370 61640
[02:40:19] L1:       ADC :24371 0
[02:40:19] RV 000A0010 5 IQ EXT: ADC End
[02:40:20] L1: RXL_I 24441 513 3
[02:40:20] L1: RXL_I 24441 513 3
[02:40:20] L1: BAND_R 8
[02:40:20] L1: BAND_C
[02:40:20] L1:  FSL: 24442 2 osload 0
[02:40:20] L1: RXL_R 24457 61640
[02:40:20] L1:       ADC :24458 0
[02:40:20] L1:  FSL: 24458 L1S
[02:40:20] RV 000A0010 5 IQ EXT: ADC End
[02:40:20] L1: Warning : IQ LOW 24475 200
[02:40:20] L1: > CPU 24475 15
[02:40:20] L1: >  PM 24475 200 0 24476 24475 0 0 43528 200
[02:40:20] L1: > !PM 24476 200 0 24477 24476 0 0 43528
[02:40:20] L1: Warning : IQ LOW 24478 200
[02:40:20] L1: >  PM 24478 200 0 24479 24478 0 0 43528 200
[02:40:20] L1: > !PM 24479 200 0 24480 24479 0 0 43528
[02:40:20] L1: RXL_I 24528 513 4
[02:40:20] L1: RXL_I 24528 513 4
[02:40:20] L1: BAND_R 6
[02:40:20] L1: BAND_C
[02:40:20] L1:  FSL: 24529 2 osload 0
[02:40:20] L1: RXL_R 24544 61640
[02:40:20] L1:       ADC :24545 0
[02:40:20] L1:  FSL: 24545 L1S
[02:40:20] RV 000A0010 5 IQ EXT: ADC End
[02:40:20] L1: Warning : IQ LOW 24558 200
[02:40:20] L1: >  PM 24558 200 0 24559 24558 0 0 43528 200
[02:40:20] L1: > !PM 24559 200 0 24560 24559 0 0 43528
[02:40:21] L1: RXL_I 24615 513 5
[02:40:21] L1: RXL_I 24615 513 5
[02:40:21] + (1024 519)(1288 774)(65287 770)(0 256)(257 257)(256 256)(257 256)(41288 259)(12200 256)(16682 19794)
[02:40:21] L1: BAND_R 8
[02:40:21] L1: BAND_C
[02:40:21] L1:  FSL: 24616 2 osload 0
[02:40:21] L1: RXL_R 24631 61640
[02:40:21] L1:       ADC :24632 0
[02:40:21] L1:  FSL: 24632 L1S
[02:40:21] RV 000A0010 5 IQ EXT: ADC End
[02:40:21] L1: RXL_I 24702 513 1
[02:40:21] L1: RXL_I 24702 513 1
[02:40:21] L1: BAND_R 6
[02:40:21] L1: BAND_C
[02:40:21] L1:  FSL: 24703 2 osload 0
[02:40:21] L1: RXL_R 24718 61640
[02:40:21] L1:       ADC :24719 0
[02:40:21] L1:  FSL: 24719 L1S
[02:40:21] RV 000A0010 5 IQ EXT: ADC End
[02:40:21] L1: Warning : IQ LOW 24726 200
[02:40:21] L1: >  PM 24726 200 0 24727 24726 0 0 43528 200
[02:40:21] L1: > !PM 24727 200 0 24728 24727 0 0 43528
[02:40:21] L1: Warning : IQ LOW 24746 200
[02:40:21] L1: >  PM 24746 200 0 24747 24746 0 0 43528 200
[02:40:21] L1: > !PM 24747 200 0 24748 24747 0 0 43528
[02:40:21] L1: RXL_I 24789 513 2
[02:40:21] L1: RXL_I 24789 513 2
[02:40:21] L1: BAND_R 8
[02:40:21] L1: BAND_C
[02:40:21] L1:  FSL: 24790 2 osload 0
[02:40:21] L1: RXL_R 24805 61640
[02:40:21] L1:       ADC :24806 0
[02:40:21] L1:  FSL: 24806 L1S
[02:40:21] RV 000A0010 5 IQ EXT: ADC End
[02:40:21] L1: Warning : IQ LOW 24820 200
[02:40:21] L1: >  PM 24820 200 0 24821 24820 0 0 43528 200
[02:40:21] L1: > !PM 24821 200 0 24822 24821 0 0 43528
[02:40:22] L1: Warning : IQ LOW 24853 200
[02:40:22] L1: >  PM 24853 200 0 24854 24853 0 0 43528 200
[02:40:22] L1: > !PM 24854 200 0 24855 24854 0 0 43528
[02:40:22] L1: RXL_I 24876 513 3
[02:40:22] L1: RXL_I 24876 513 3
[02:40:22] L1: BAND_R 6
[02:40:22] L1: BAND_C
[02:40:22] L1:       ADC :24887 0
[02:40:22] RV 000A0010 5 IQ EXT: ADC End
[02:40:22] L1:  FSL: 24888 2 osload 0
[02:40:22] L1: RXL_R 24892 61640
[02:40:22] L1:       ADC :24893 0
[02:40:22] L1:  FSL: 24893 L1S
[02:40:22] RV 000A0010 5 IQ EXT: ADC End
[02:40:22] L1: Warning : IQ LOW 24917 200
[02:40:22] L1: >  PM 24917 200 0 24918 24917 0 0 43528 200
[02:40:22] L1: > !PM 24918 200 0 24919 24918 0 0 43528
[02:40:22] L1: RXL_I 24963 513 4
[02:40:22] L1: RXL_I 24963 513 4
[02:40:22] L1: BAND_R 8
[02:40:22] L1: BAND_C
[02:40:22] L1:  FSL: 24964 2 osload 0
[02:40:22] L1:  FSL: 24968 L1S
[02:40:22] L1: RXL_R 24979 61640
[02:40:22] L1:       ADC :24980 0
[02:40:22] RV 000A0010 5 IQ EXT: ADC End
[02:40:23] L1: RXL_I 25050 513 5
[02:40:23] L1: RXL_I 25050 513 5
[02:40:23] + (1024 519)(1288 774)(65287 770)(0 256)(257 257)(256 256)(257 256)(41288 259)(12200 256)(16682 19794)
[02:40:23] L1:  FSL: 25051 2 osload 0
[02:40:23] L1: LOS_R 25054
[02:40:23] GPF trace id=A7 ts=0001C4F8 RR->PCO tc=07 "Unexpected sync event"
[02:40:23] GPF trace id=A7 ts=0001C4F8 SYST->PCO tc=07 "TRACE ERROR in RR"
[02:40:23] L1:  FSL: 25070 L1S
[02:40:23] L1:       ADC :25091 0
[02:40:23] RV 000A0010 5 IQ EXT: ADC End
[02:40:23] L1:  FSL: 25092 2 osload 0
[02:40:23] L1:  FSL: 25172 L1S
[02:40:23] L1:       ADC :25193 0
[02:40:23] RV 000A0010 5 IQ EXT: ADC End
[02:40:23] L1:  FSL: 25194 2 osload 0
[02:40:24] L1:  FSL: 25274 L1S
[02:40:24] L1: > CPU 25195 4
[02:40:24] L1:       ADC :25295 0
[02:40:24] RV 000A0010 5 IQ EXT: ADC End
[02:40:24] L1:  FSL: 25296 2 osload 0
[02:40:24] L1: > CPU 25296 5
[02:40:24] L1:  FSL: 25376 L1S
[02:40:24] L1:       ADC :25397 0
[02:40:24] RV 000A0010 5 IQ EXT: ADC End
[02:40:24] L1:  FSL: 25398 2 osload 0
[02:40:24] L1:  FSL: 25478 L1S
[02:40:25] L1:       ADC :25499 0
[02:40:25] RV 000A0010 5 IQ EXT: ADC End
[02:40:25] L1:  FSL: 25500 2 osload 0
[02:40:25] L1:  FSL: 25580 L1S
[02:40:25] L1:       ADC :25601 0
[02:40:25] RV 000A0010 5 IQ EXT: ADC End
[02:40:25] L1:  FSL: 25602 2 osload 0
[02:40:25] L1:  FSL: 25682 L1S
[02:40:26] L1:       ADC :25703 0
[02:40:26] RV 000A0010 5 IQ EXT: ADC End
[02:40:26] L1:  FSL: 25704 2 osload 0
[02:40:26] L1:  FSL: 25784 L1S
[02:40:26] L1:       ADC :25805 0
[02:40:26] RV 000A0010 5 IQ EXT: ADC End
[02:40:26] L1:  FSL: 25806 2 osload 0
[02:40:26] L1:  FSL: 25886 L1S
[02:40:26] L1:       ADC :25907 0
[02:40:26] RV 000A0010 5 IQ EXT: ADC End
[02:40:26] L1:  FSL: 25908 2 osload 0
[02:40:27] RV 00000000 1 RVT: System Time 0000659A
[02:40:27] L1:  FSL: 25988 L1S
[02:40:27] L1:       ADC :26009 0
[02:40:27] RV 000A0010 5 IQ EXT: ADC End
[02:40:27] L1:  FSL: 26010 2 osload 0
[02:40:27] L1:  FSL: 26090 L1S
[02:40:27] L1:       ADC :26111 0
[02:40:27] RV 000A0010 5 IQ EXT: ADC End
[02:40:27] L1:  FSL: 26112 2 osload 0
[02:40:28] L1:  FSL: 26192 L1S
[02:40:28] L1:       ADC :26213 0
[02:40:28] RV 000A0010 5 IQ EXT: ADC End
[02:40:28] L1:  FSL: 26214 2 osload 0
[02:40:28] L1:  FSL: 26294 L1S
[02:40:28] L1:       ADC :26315 0
[02:40:28] RV 000A0010 5 IQ EXT: ADC End
[02:40:28] L1:  FSL: 26316 2 osload 0
[02:40:29] L1:  FSL: 26411 L1S
[02:40:33] L1: BAND_R 6
[02:40:33] L1: BAND_C
[02:40:33] L1: RXL_R 27223 61640
[02:40:33] L1:       ADC :27225 0
[02:40:33] L1: > CPU 27225 9
[02:40:33] RV 000A0010 5 IQ EXT: ADC End
[02:40:33] L1: Warning : IQ LOW 27232 200
[02:40:33] L1: > CPU 27232 15
[02:40:33] L1: >  PM 27232 200 0 27233 27232 0 0 43528 200
[02:40:33] L1: > !PM 27233 200 0 27234 27233 0 0 43528
[02:40:33] L1: Warning : IQ LOW 27253 200
[02:40:33] L1: >  PM 27253 200 0 27254 27253 0 0 43528 200
[02:40:33] L1: > !PM 27254 200 0 27255 27254 0 0 43528
[02:40:33] L1: RXL_I 27295 513 1
[02:40:33] L1: RXL_I 27295 513 1
[02:40:33] L1: BAND_R 8
[02:40:33] L1: BAND_C
[02:40:33] L1:  FSL: 27296 2 osload 0
[02:40:33] L1: RXL_R 27311 61640
[02:40:33] L1:       ADC :27312 0
[02:40:33] L1:  FSL: 27312 L1S
[02:40:33] RV 000A0010 5 IQ EXT: ADC End
[02:40:33] L1: RXL_I 27382 513 2
[02:40:33] L1: RXL_I 27382 513 2
[02:40:33] L1: BAND_R 6
[02:40:33] L1: BAND_C
[02:40:33] L1:  FSL: 27383 2 osload 0
[02:40:34] L1: RXL_R 27398 61640
[02:40:34] L1:       ADC :27399 0
[02:40:34] L1:  FSL: 27399 L1S
[02:40:34] RV 000A0010 5 IQ EXT: ADC End
[02:40:34] L1: RXL_I 27469 513 3
[02:40:34] L1: RXL_I 27469 513 3
[02:40:34] L1: BAND_R 8
[02:40:34] L1: BAND_C
[02:40:34] L1:  FSL: 27470 2 osload 0
[02:40:34] L1: RXL_R 27485 61640
[02:40:34] L1:       ADC :27486 0
[02:40:34] L1:  FSL: 27486 L1S
[02:40:34] RV 000A0010 5 IQ EXT: ADC End
[02:40:34] L1: Warning : IQ LOW 27541 200
[02:40:34] L1: >  PM 27541 200 0 27542 27541 0 0 43528 200
[02:40:34] L1: > !PM 27542 200 0 27543 27542 0 0 43528
[02:40:34] L1: RXL_I 27556 513 4
[02:40:34] L1: RXL_I 27556 513 4
[02:40:34] L1: BAND_R 6
[02:40:34] L1: BAND_C
[02:40:34] L1:  FSL: 27557 2 osload 0
[02:40:34] L1: RXL_R 27572 61640
[02:40:34] L1:       ADC :27573 0
[02:40:34] L1:  FSL: 27573 L1S
[02:40:34] RV 000A0010 5 IQ EXT: ADC End
[02:40:35] L1: Warning : IQ LOW 27629 200
[02:40:35] L1: >  PM 27629 200 0 27630 27629 0 0 43528 200
[02:40:35] L1: > !PM 27630 200 0 27631 27630 0 0 43528
[02:40:35] L1: RXL_I 27643 513 5
[02:40:35] L1: RXL_I 27643 513 5
[02:40:35] + (1024 519)(1288 774)(65287 770)(0 256)(257 257)(256 256)(257 256)(41288 259)(12200 256)(16682 19794)
[02:40:35] L1: BAND_R 8
[02:40:35] L1: BAND_C
[02:40:35] L1:  FSL: 27644 2 osload 0
[02:40:35] L1: RXL_R 27659 61640
[02:40:35] L1:       ADC :27660 0
[02:40:35] L1:  FSL: 27660 L1S
[02:40:35] RV 000A0010 5 IQ EXT: ADC End
[02:40:35] L1: RXL_I 27730 513 1
[02:40:35] L1: RXL_I 27730 513 1
[02:40:35] L1: BAND_R 6
[02:40:35] L1: BAND_C
[02:40:35] L1:       ADC :27743 0
[02:40:35] RV 000A0010 5 IQ EXT: ADC End
[02:40:35] L1:  FSL: 27744 2 osload 0
[02:40:35] L1: RXL_R 27746 61640
[02:40:35] L1:       ADC :27747 0
[02:40:35] L1:  FSL: 27747 L1S
[02:40:35] RV 000A0010 5 IQ EXT: ADC End
[02:40:35] L1: Warning : IQ LOW 27777 200
[02:40:35] L1: >  PM 27777 200 0 27778 27777 0 0 43528 200
[02:40:35] L1: > !PM 27778 200 0 27779 27778 0 0 43528
[02:40:35] L1: RXL_I 27817 513 2
[02:40:35] L1: RXL_I 27817 513 2
[02:40:35] L1: BAND_R 8
[02:40:35] L1: BAND_C
[02:40:36] L1:  FSL: 27818 2 osload 0
[02:40:36] L1:  FSL: 27824 L1S
[02:40:36] L1: RXL_R 27833 61640
[02:40:36] L1:       ADC :27834 0
[02:40:36] RV 000A0010 5 IQ EXT: ADC End
[02:40:36] L1: Warning : IQ LOW 27864 200
[02:40:36] L1: > CPU 27864 15
[02:40:36] L1: >  PM 27864 200 0 27865 27864 0 0 43528 200
[02:40:36] L1: > !PM 27865 200 0 27866 27865 0 0 43528
[02:40:36] L1: RXL_I 27904 513 3
[02:40:36] L1: RXL_I 27904 513 3
[02:40:36] L1: BAND_R 6
[02:40:36] L1: BAND_C
[02:40:36] L1:  FSL: 27905 2 osload 0
[02:40:36] L1: RXL_R 27920 61640
[02:40:36] L1:       ADC :27921 0
[02:40:36] L1:  FSL: 27921 L1S
[02:40:36] RV 000A0010 5 IQ EXT: ADC End
[02:40:36] L1: Warning : IQ LOW 27924 200
[02:40:36] L1: >  PM 27924 200 0 27925 27924 0 0 43528 200
[02:40:36] L1: > !PM 27925 200 0 27926 27925 0 0 43528
[02:40:36] L1: Warning : IQ LOW 27981 200
[02:40:36] L1: >  PM 27981 200 0 27982 27981 0 0 43528 200
[02:40:36] L1: > !PM 27982 200 0 27983 27982 0 0 43528
[02:40:36] L1: RXL_I 27991 513 4
[02:40:36] L1: RXL_I 27991 513 4
[02:40:36] L1: BAND_R 8
[02:40:36] L1: BAND_C
[02:40:36] L1:  FSL: 27992 2 osload 0
[02:40:36] L1: RXL_R 28007 61640
[02:40:36] L1:       ADC :28008 0
[02:40:36] L1:  FSL: 28008 L1S
[02:40:36] RV 000A0010 5 IQ EXT: ADC End
[02:40:37] L1: RXL_I 28078 513 5
[02:40:37] L1: RXL_I 28078 513 5
[02:40:37] + (1024 519)(1288 774)(65287 770)(0 256)(257 257)(256 256)(257 256)(41288 259)(12200 256)(16682 19794)
[02:40:37] L1:  FSL: 28079 2 osload 0
[02:40:37] L1: LOS_R 28082
[02:40:37] L1:  FSL: 28130 L1S
[02:40:37] L1:       ADC :28151 0
[02:40:37] RV 000A0010 5 IQ EXT: ADC End
[02:40:37] L1:  FSL: 28152 2 osload 0
[02:40:37] L1:  FSL: 28232 L1S
[02:40:38] L1:       ADC :28253 0
[02:40:38] RV 000A0010 5 IQ EXT: ADC End
[02:40:38] L1:  FSL: 28254 2 osload 0
[02:40:38] L1:  FSL: 28334 L1S
[02:40:38] L1:       ADC :28355 0
[02:40:38] RV 000A0010 5 IQ EXT: ADC End
[02:40:38] L1:  FSL: 28356 2 osload 0
[02:40:38] L1:  FSL: 28436 L1S
[02:40:38] L1:       ADC :28457 0
[02:40:38] RV 000A0010 5 IQ EXT: ADC End
[02:40:38] L1:  FSL: 28458 2 osload 0
[02:40:39] L1:  FSL: 28553 L1S