Glue logic ICs common to SDSL and IDSL:

Area between MC68LC302 and the LEDs:

HC139 -- dual 2-to-4 decoder, perfect active-low chip select splitter.
	Must be for CS2.
AC374 -- 8-bit register, rising edge-triggered, 3-state outputs with OE, no
	async inputs. This must be the LED register.

Area between MC68LC302 and Ethernet:

HC04   -- 6 inverters
	slot 1 SDSL: inverts BCLK from bitpump to NMSI
	slot 2 SDSL: used for PA10
	slot 3 inverts Ethernet IRQ (CS8900 has active high IRQ output)
	slot 4 IDSL: inverts FSR/FSC output from MC145572, out to G1 of HCT125
	others unused
HC32   -- 4 non-inverting OR gates. Acts as AND with active-low inputs
	and outputs for Ethernet ISA emulation:
	slot 1 produces MEMR
	slot 2 produces IOR
	slot 3 produces MEMW
	slot 4 produces IOW
	A inputs are CS, B inputs are R/W strobes
HCT125 -- 4 non-inverting 3-state buffers, enable active low.
	slot 1: SDSL: A1 wired to PA9, G1 and Y1 couldn't be traced
		IDSL: A1 wired to DCL output from MC145572, gated by FSR/FSC,
			output to HCT74 DFF
	slot 2: input grounded, output M68K_HALT,
		enable driven by master reset net
	slot 3: IDSL: gates 4.096 MHz clock from MC145572 to LC302,
		enable pulled to GND through 100 ohm resistor
	slot 4: input grounded, output M68K_RESET,
		enable driven by master reset net

Reset logic:

The primary reset source is DS1233 power supply monitor, drives active low
master reset net through a 5 kOhm resistor, which then pulls M68K_HALT and
M68K_RESET low via the HCT125.
The WDOG output is also connected to the master reset net.

MC145572 RESET on IDSL is connected to the DS1233 output before the resistor.

On IDSL version only:

An HCT74 dual DFF close to MC145572, only one slot used, produces the PCM
envelope sync signal for the LC302. Async set driven by HCT125 slot 1, D tied
low, clock is the TSEN output.

Interrupts:

IRQ1 is Bt8970 on the SDSL version, MC145572 on IDSL.
IRQ6 is Ethernet, driven by CS8900 INTRQ0 pin through HC04 slot 3.
IRQ7 is unused.

GPIO A:

Pin	Usage
PA0	SCC2 RxD
PA1	SCC2 TxD
PA2	SDSL: Output goes to ICD2053 DATA input + pullup
	IDSL: pullup
PA3	Output, init to 1 -- unused? Pullup in hardware on both versions.
PA4	SDSL: Input, strapping option indicating the type of hardware:
	0 is CopperRocket-SDSL
	1 is some SDSL prototype hardware
	IDSL: SCPEN output, has pullup
PA5	Output connected to CS8900 HWSLEEP pin
PA6	Output connected to CS8900 RESET pin
PA7	Output, LED blanking control, 0 enables. Wired to OE pin of the '374.
PA8	SDSL: Probable relic. In the cr201s-boot firmware it starts out as an
	input, then becomes output asserted during a symbol delay (0F828).
	IDSL: SPRxD
PA9	SDSL: Output, init to 1, goes to the HCT125, then unclear, probable
	relic.
	IDSL: SPTxD
PA10	SDSL: Output, init to 1, goes to the 2A input of HC04, then to nowhere
	it seems, probable relic.
	IDSL: SPCLK
PA12	MODCLK, doesn't seem to have other uses

PA<11:8> have pullups on the SDSL version.

GPIO B:

Pin	Usage
PB3	Used on another HW rev together with PB5 to control bitpump clock MUX
	Pullup on both CopperRockets
PB5	SDSL: Output goes to ICD2053 SCLK input + pullup
	IDSL: pullup
PB6	Left as input by cr201s-boot firmware, traced to an unpopulated
	footprint
	Pullup on both CopperRockets
PB7	WDOG
PB8	Input -- LANLED from CS8900
PB9	cr201s-boot firmware: Input HTU-C mode speed select bit 0
PB10	cr201s-boot firmware: Input HTU-C mode speed select bit 1
PB11	cr201s-boot firmware: Input HTU-C mode speed select bit 2

PB9 and PB10 have been traced to an unpopulated IC footprint,
PB11 has been traced to unpopulated SW1.
PB<11:9> have pullups on both CopperRockets.
