#ifndef  HOST_HW_DEFS_H         
#define  HOST_HW_DEFS_H         

/* host registers */
#define 	 HW_HOST_IRR_REG_ADDR 		 0x0A00UL          
#define 	 HW_HOST_IMR_REG_ADDR 		 0x0A04UL          
#define 	 HW_HOST_ICR_REG_ADDR 		 0x0A08UL          
#define 	 HW_HOST_SEP_SRAM_THRESHOLD_REG_ADDR 		 0x0A10UL          
#define 	 HW_HOST_SEP_BUSY_REG_ADDR 		 0x0A14UL          
#define 	 HW_HOST_SEP_SW_MONITOR_LOW_REG_ADDR 		 0x0A20UL          
#define 	 HW_HOST_SEP_SW_MONITOR_HIGH_REG_ADDR 		 0x0A24UL          
#define 	 HW_HOST_SEP_HOST_FLOW_ACK_REG_ADDR 		 0x0A28UL          
#define 	 HW_HOST_CC_SW_RST_REG_ADDR 		 0x0A40UL          
#define 	 HW_HOST_SEP_SW_RST_REG_ADDR 		 0x0A44UL          
#define 	 HW_HOST_FLOW_DMA_SW_INT0_REG_ADDR 		 0x0A80UL          
#define 	 HW_HOST_FLOW_DMA_SW_INT1_REG_ADDR 		 0x0A84UL          
#define 	 HW_HOST_FLOW_DMA_SW_INT2_REG_ADDR 		 0x0A88UL          
#define 	 HW_HOST_FLOW_DMA_SW_INT3_REG_ADDR 		 0x0A8cUL          
#define 	 HW_HOST_FLOW_DMA_SW_INT4_REG_ADDR 		 0x0A90UL          
#define 	 HW_HOST_FLOW_DMA_SW_INT5_REG_ADDR 		 0x0A94UL          
#define 	 HW_HOST_FLOW_DMA_SW_INT6_REG_ADDR 		 0x0A98UL          
#define 	 HW_HOST_FLOW_DMA_SW_INT7_REG_ADDR 		 0x0A9cUL          
#define 	 HW_HOST_SEP_HOST_GPR0_REG_ADDR 		 0x0B00UL          
#define 	 HW_HOST_SEP_HOST_GPR1_REG_ADDR 		 0x0B04UL          
#define 	 HW_HOST_SEP_HOST_GPR2_REG_ADDR 		 0x0B08UL          
#define 	 HW_HOST_SEP_HOST_GPR3_REG_ADDR 		 0x0B0CUL          
#define 	 HW_HOST_SEP_HOST_GPR0_RST_REG_ADDR 		 0x0B10UL          
#define 	 HW_HOST_SEP_HOST_GPR1_RST_REG_ADDR 		 0x0B14UL          
#define 	 HW_HOST_SEP_HOST_GPR2_RST_REG_ADDR 		 0x0B18UL          
#define 	 HW_HOST_SEP_HOST_GPR3_RST_REG_ADDR 		 0x0B1CUL          
#define 	 HW_HOST_SEP_HOST_GPR4_REG_ADDR 		 0x0B20UL          
#define 	 HW_HOST_SEP_HOST_GPR4_RST_REG_ADDR 		 0x0B24UL          
#define 	 HW_HOST_HOST_SEP_GPR0_REG_ADDR 		 0x0B80UL          
#define 	 HW_HOST_HOST_SEP_GPR1_REG_ADDR 		 0x0B84UL          
#define 	 HW_HOST_HOST_SEP_GPR2_REG_ADDR 		 0x0B88UL          
#define 	 HW_HOST_HOST_SEP_GPR3_REG_ADDR 		 0x0B8CUL          
#define 	 HW_HOST_HOST_ENDIAN_REG_ADDR 		 0x0B90UL          
#define 	 HW_HOST_HOST_COMM_CLK_EN_REG_ADDR 		 0x0B94UL          
#define 	 HW_HOST_HOST_SEP_GPR4_REG_ADDR 		 0x0B98UL          
#define 	 HW_SRAM_DATA_REG_ADDR 		 0x0F00UL          
#define 	 HW_SRAM_ADDR_REG_ADDR 		 0x0F04UL          
#define 	 HW_SRAM_DATA_READY_REG_ADDR 		 0x0F08UL
#endif                          
