MegaCore(R) IP Library version 6.0 Readme file
===============================================================

This file for the Altera(R) MegaCore IP Library CD-ROM 
contains the following information:

MegaCore IP Library Overview
MegaCore IP Library Contents


MegaCore IP Library Overview
===============================================================
The MegaCore IP Library CD-ROM contains the MegaCore IP Library 
outlined in the MegaCore IP Library Contents section.

For new features, installation instructions, and system 
requirements for the MegaCore IP Library, refer to the release 
notes file rn_megacore_library_600.pdf in the top-level 
directory of the MegaCore IP Library CDROM. Each MegaCore 
function has its own release notes in the /doc directory for the 
MegaCore function. 

For a list of known issues in this release, refer to the 
specific errata sheet for each individual MegaCore function on 
the Altera website at
 
	http://www.altera.com/literature/lit-es.jsp


MegaCore IP Library Contents
===============================================================
The list below briefly describes the Altera MegaCore functions 
included on the MegaCore IP Library CD-ROM. For details about 
these MegaCore functions, visit the Altera IP Megastore at the 
following URL:

	http://www.altera.com/products/ip 


2D FIR Filter                                              v1.0.0
---------------------------------------------------------------------
The Altera 2D FIR Filter MegaCore function is part of the Video and 
Image Processing Suite. This MegaCore function provides a flexible 
and efficient means to perform 2D finite impulse response (FIR) 
filtering operations using matrices of 33, 55, or 7x7 constant 
coefficients and is suitable for use in a wide variety of image 
processing and display applications.

Device families supported by the 2D FIR Filter include 
Stratix (R) II, Stratix II GX, Stratix GX, Stratix, HardCopy(R) II, 
and Cyclone(TM) II. 


2D Median Filter                                           v1.0.0
---------------------------------------------------------------------
The Altera 2D Median Filter MegaCore function is part of the Video 
and Image Processing Suite. This MegaCore function provides a flexible 
and efficient means to perform 2D median filtering operations using 
matrices of 33, 5x5, or 7x7 kernels and is suitable for use in a 
wide variety of image processing and display applications.	

Device families supported by the 2D Median Filter include Stratix II, 
Stratix GX, Stratix II GX, Stratix, HardCopy II, and Cyclone II.


8B10B Encoder/Decoder                                      v1.6.1
---------------------------------------------------------------------
The Altera 8B10B Encoder/Decoder is a compact, high performance 
MegaCore function for physical layer coding for Gigabit Ethernet, 
Fibre Channel and other multigigabit applications. 

Device families supported by the 8B10B Encoder/Decoder include 
Stratix II, Stratix II GX, Stratix GX, Stratix, HardCopy II, 
HardCopy Stratix, Cyclone II, and Cyclone. 


Alpha Blending Mixer                                       v1.0.0
----------------------------------------------------------------------
The Altera Alpha Blending Mixer MegaCore function is part of the Video 
and Image Processing Suite. This MegaCore function provides an 
efficient means to mix together up to eight image layers. It provides 
support for both picture-in-picture mixing and image blending, and is 
suitable for use in a wide variety of image processing and display 
applications.

Device families supported by the Alpha Blending Mixer include 
Stratix II, Stratix II GX, Stratix GX, Stratix, HardCopy II, and 
Cyclone II. 


ASI                                                        v1.0.0
---------------------------------------------------------------------
The Altera Asynchronous Serial Interface (ASI) MegaCore function is a 
full-duplex digital video broadcast asynchronous serial interface 
(DVB-ASI) that transports MPEG-2 packets over copper-based cables or 
optical networks. Broadcast facilities use DVB-ASI as a serial link 
between equipment.

Device families supported by ASI include Stratix II, Stratix II GX,
Stratix GX, HardCopy II, Cyclone II, and Cyclone. 


Color Space Converter                                      v3.0.0
---------------------------------------------------------------------
The Altera Color Space Converter MegaCore function is part of the 
Video and Image Processing Suite. This MegaCore function provides a 
flexible and efficient means to convert video or image data from one 
color space to another and is suitable for use in a wide variety of 
image processing and display applications. 

Device families supported by the Color Space Converter include 
Stratix II, Stratix II GX, Stratix GX, Stratix, HardCopy II, and 
Cyclone II. 


Chroma Resampler                                           v1.0.0
---------------------------------------------------------------------
The Altera Chroma Resampler MegaCore function is part of the Video 
and Image Processing Suite. This MegaCore function converts the 
sampling rate of the chroma data for image frames and is suitable for 
use in a wide variety of image processing and display applications.
	
Device families supported by the Chroma Resampler include Stratix II, 
Stratix II GX, Stratix GX, Stratix, HardCopy II, and Cyclone II. 


DDR & DDR2 SDRAM Controller                                v3.4.0
---------------------------------------------------------------------
The Altera DDR & DDR2 SDRAM Controller includes two MegaCore 
functions, the DDR SDRAM Controller and DDR2 SDRAM Controller. These 
handle the complex aspects of using DDR & DDR2 SDRAM such as 
performing double data rate functionality, initializing the memory 
devices, managing SDRAM banks, and keeping the devices refreshed at 
appropriate intervals. Read and write requests are translated from 
the local interface into all the necessary SDRAM command signals.

Device families supported by the DDR SDRAM Controller include 
Stratix II, Stratix II GX, Stratix GX, Stratix, Hardcopy II, 
Cyclone II, and Cyclone. 

Device families supported for the DDR2 SDRAM Controller include 
Stratix II, Stratix II GX, HardCopy II, and Cyclone II. 


Deinterlacer                                               v1.0.0
---------------------------------------------------------------------
The Altera Deinterlacer MegaCore function is part of the Video and 
Image Processing Suite. This MegaCore function provides a flexible 
and efficient means to convert interlaced video to progressive video 
using bob and weave algorithms and is suitable for use in a wide 
variety of image processing and display applications.

Device families supported by the Deinterlacer include Stratix II, 
Stratix II GX, Stratix GX, Stratix, HardCopy II, and Cyclone II. 


FFT                                                        v2.2.1
---------------------------------------------------------------------
The Altera FFT (Fast Fourier Transform) MegaCore function is a high 
performance, highly-parameterizable FFT/IFFT processor. The FFT 
MegaCore function implements a Radix-2/4 decimation-in-frequency (DIF) 
FFT algorithm for transform lengths of 2**m where 6 <= m <= 14, 
internally using a block-floating-point architecture to maximize 
signal dynamic range in the transform calculation.

Device families supported by FFT include Stratix II, Stratix II GX, 
Stratix GX, Stratix, HardCopy II, HardCopy Stratix, Cyclone II, 
and Cyclone. 


FIR Compiler                                               v3.3.1
---------------------------------------------------------------------
The Altera FIR Compiler MegaCore function generates finite impulse 
response (FIR) filters optimized for Altera devices. You can specify 
a variety of filter architectures, including fully parallel, serial, 
multibit serial fixed-coefficient, multicycle variable, and multirate 
filters. The FIR Compiler includes a coefficient generator.

Device families supported by the FIR Compiler include Stratix II, 
Stratix II GX, Stratix GX, Stratix, HardCopy II, HardCopy Stratix, 
Cyclone II, and Cyclone. 


Gamma Corrector                                            v1.0.0
---------------------------------------------------------------------
The Altera Gamma Corrector MegaCore function is part of the Video and 
Image Processing Suite. This MegaCore function performs Gamma 
correction on a color plane/space and is suitable for use in a wide 
variety of image processing and display applications.

Device families supported by the Gamma Corrector include Stratix II, 
Stratix II GX, Stratix GX, Stratix, HardCopy II, and Cyclone II. 
 

HyperTransport                                             v1.4.0
---------------------------------------------------------------------
The Altera HyperTransport(TM) MegaCore function implements high-speed 
packet transfers between physical (PHY) and link-layer devices, and 
is fully compliant with the HyperTransport I/O Link specification, 
Revision 1.03. This core allows designers to interface quickly and 
easily to a wide range of HyperTransport technology enabled devices, 
including network processors, co-processors, video chipsets, and 
ASICs.  

Device families supported by HyperTransport include Stratix II, 
Stratix II GX, Stratix GX, Stratix, and HardCopy Stratix.

 
Line Buffer Compiler                                       v1.0.0
---------------------------------------------------------------------
The Altera Line Buffer Compiler is part of the Video and Image 
Processing Suite. The MegaCore function that this compiler generates 
can be used to map image line buffers to Altera on-chip memories.

Device families supported by the Line Buffer Compiler include 
Stratix II, Stratix II GX, Stratix GX, Stratix, HardCopy II, and 
Cyclone II. 

    
NCO Compiler                                               v2.3.1
---------------------------------------------------------------------
The Altera NCO Compiler MegaCore function generates numerically 
controlled oscillators (NCOs) optimized for Altera devices. You can 
implement a variety of NCO architectures, including ROM-based, 
CORDIC-based, and multiplier-based. The IP Toolbench MegaWizard also 
includes time and frequency domain graphs that dynamically display 
the functionality of the NCO, based on your parameter settings.

Device families supported by NCO Compiler include Stratix II, 
Stratix II GX, Stratix GX, Stratix, HardCopy II, HardCopy Stratix, 
Cyclone II, and Cyclone. 


PCI Compiler (32- & 64-bit, Master/Target and Target-Only) v4.1.1
---------------------------------------------------------------------              
The Altera PCI Compiler provides a complete solution for
implementing PCI interfaces with Altera devices. It contains the 
Altera pci_mt64, pci_mt32, pci_t64, and pci_t32 MegaCore functions,
Verilog HDL and VHDL testbenches, plus reference designs. The Altera 
PCI MegaCore functions are optimized for Altera devices and are 
fully tested to meet the requirements of the PCI Local Bus 
Specification, Revision 3.0 and Compliance Checklist, Revision 3.0.

Device families supported by PCI Compiler include Stratix II, 
Stratix II GX, Stratix GX, Stratix, HardCopy II, HardCopy Stratix, 
Cyclone II, Cyclone, and MAX II (32-bit PCI only).


PCI Express Compiler                                       v2.1.0
---------------------------------------------------------------------
The Altera PCI Express Compiler generates customized PCI Express 
MegaCore functions you use to design PCI Express endpoints, including 
nontransparent bridges, or unique designs that combine multiple 
PCI Express components in a single Altera device. The PCI Express 
MegaCore functions are PCI Express(TM) Base Specification Revision 
1.0a or Revision 1.1 compliant, and implement all required and most 
optional features of the specification for the transaction, data 
link, and physical layers.

Device families supported by PCI Express Compiler include Stratix II, 
Stratix II GX, Stratix GX, HardCopy II, and Cyclone II. 


POS-PHY Level 2 & 3 Compiler                               v1.4.1
--------------------------------------------------------------------
The Altera POS-PHY Level 2 and 3 Compiler generates MegaCore 
functions for use in link-layer or physical (PHY) layer devices that 
transfer data to and from packet over SONET/SDH (POS) devices using 
the standard POS-PHY bus. The compiler comprises separately 
configurable modules, which can be easily combined to generate a 
highly parameterized module, allowing POS-PHY compliant interfaces 
to be included in custom designs. The compiler supports POS-PHY level 
3 operating at up to 3.2 gigabits per second (Gbps), and level 2 
operating at up to 832 megabits per second (Mbps).

Device families supported by POS-PHY Level 2 & 3 Compiler include 
Stratix II, Stratix II GX, Stratix GX, Stratix, HardCopy II, 
HardCopy Stratix, Cyclone II, and Cyclone.


POS-PHY Level 4                                            v2.4.1
--------------------------------------------------------------------
The Altera POS-PHY Level 4 MegaCore function implements the Optical 
Internetworking Forum (OIF) System Packet Interface Level 4 Phase 2 
(SPI-4.2) for cell and packet transfers between devices in 
multigigabit applications, including: OC-192/STM-64 ATM and packet 
over SONET/SDH, 10 Gigabit Ethernet, and multichannel Fast & Gigabit 
Ethernet. You can generate Single-PHY and Multi-PHY configurations 
(up to 256-ports) with LVDS rates up to 1 Gbps with embedded Dynamic 
Phase Alignment (DPA).

Device families supported by POS-PHY Level 4 include Stratix II, 
Stratix II GX, Stratix GX, Stratix, HardCopy II, HardCopy Stratix, 
Cyclone II, and Cyclone.


QDRII SRAM Controller                                      v1.3.0
--------------------------------------------------------------------
The Altera QDRII SRAM Controller MegaCore function handles the 
various aspects of using QDRII SRAM such as generating the SRAM 
clocks, driving QDR write data, and capturing DDR read data. The 
QDRII SRAM Controller MegaCore function translates read and write 
requests from the local interface into all the necessary SRAM 
command signals.

Device families supported by QDRII SRAM Controller include 
Stratix II, Stratix II GX, Stratix GX, Stratix, and HardCopy II.


RapidIO                                                    v3.1.0
---------------------------------------------------------------------
The Altera RapidIO MegaCore function generates the interconnect logic
to pass control and data between microprocessors, digital signal 
processors (DSPs), communications and network processors, system 
memories, and peripheral devices. You can implement 8-bit 
source-synchronous (parallel) RapidIO interfaces with integrated 
Dynamic Phase Alignment (DPA) at up to 1 Gbps, or serial RapidIO 
interfaces with embedded clock-data recovery (CDR) supporting both 
1x/4x serial RapidIO interfaces with embedded clock-data recovery 
(CDR) at up to 3.125 Gbps in Stratix GX and 6.375 Gbps in 
Stratix II GX. The RapidIO MegaCore function is targeted for 
high-performance, multicomputing, high-bandwidth input/output 
applications.

Device families supported by RapidIO include Stratix II, 
Stratix II GX, Stratix GX, Stratix, HardCopy II, Hardcopy Stratix, 
and Cyclone II. 


Reed-Solomon Compiler (Decoder & Encoder)                  v4.1.0
--------------------------------------------------------------------
The Altera Reed-Solomon Compiler consists of a fully parameterizable 
encoder and decoder for forward error correction applications. The  
Reed-Solomon Compiler has the following options:

   Erasures-supporting option: the RS decoder can correct symbol 
   errors up to the number of check symbols, if you give the 
   location of the errors to the decoder.

   Variable encoding or decoding: you can vary the total number of 
   symbols per codeword and the number of check symbols, in real 
   time, from their minimum allowable values up to their selected 
   values, when you are encoding or decoding.

   Error symbol output: the RS decoder finds the error values and 
   location and adds these values in the Galois field to the input 
   value.

   Bit error output: either split count or full count. 

Device families supported by the Reed-Solomon Compiler include 
Stratix II, Stratix II GX, Stratix GX, Stratix, Hardcopy II, 
HardCopy Stratix, Cyclone II, and Cyclone.


RLDRAM II Controller                                       v1.1.0
--------------------------------------------------------------------
The Altera RLDRAM II Controller MegaCorefunction handles the 
complex aspects of using RLDRAM IIinitializing the memory devices 
and translating read and write requests from the local interface into 
all the necessary RLDRAM II command signals.
 
Device families supported by the RLDRAM II Controller include 
Stratix II, Stratix II GX, and HardCopy II.


SDI                                                        v1.0.0
---------------------------------------------------------------------
The Altera Serial Digital Interface (SDI) MegaCore function is a 
full-duplex SDI, providing support for standard definition SMPTE 259 
(SD) and high definition SMPTE 292 (HD) links at 270 Mbps and 1.5 
Gbps respectively.

Device families supported by the SDI include Stratix II, 
Stratix II GX, Stratix GX, HardCopy II, Cyclone II, and Cyclone. 


Scaler                                                     v1.0.0
---------------------------------------------------------------------
The Altera Scaler MegaCore function is part of the Video and Image 
Processing Suite. This MegaCore function provides an efficient means 
to resize image frames using either bilinear filtering or nearest 
neighbor scaling and is suitable for use in a wide variety of image 
processing and display applications.

Device families supported by Scaler include Stratix II, 
Stratix II GX, Stratix GX, Stratix, HardCopy II, and Cyclone II.


SerialLite II                                              v1.1.0
--------------------------------------------------------------------
The Altera SerialLite MegaCore function is a simple, high-speed, 
low-latency, low-resource, point-to-point serial data communication 
link. It implements the full SerialLite protocol with performance up 
to 3.125 Gbps in Stratix GX and 6.375 Gbps in Stratix II GX across 
the serial data communication link. It is highly configurable, 
providing a wide range of functionality suited to moving data in 
many different environments.

Device families supported by SerialLite II include Stratix II GX and 
Stratix GX.


UTOPIA Level 2 Master                                      v2.4.1
--------------------------------------------------------------------
The Altera UTOPIA Level 2 Master MegaCore function is designed for 
use in ATM layer devices that transfer data to and from PHY devices 
using the standard UTOPIA bus. The UTOPIA Level 2 Master MegaCore 
function comprises a separate transmitter and receiver; both support 
SPHY and MPHY operation modes. SPHY mode supports octet- or 
cell-level handshake; MPHY mode supports cell-level handshake with 
up to 31 PHY devices.

Device families supported by UTOPIA Level 2 Master include 
Stratix II, Stratix II GX, Stratix GX, Stratix, HardCopy II, 
HardCopy Stratix, Cyclone II, and Cyclone.


UTOPIA Level 2 Slave                                       v2.5.1
--------------------------------------------------------------------
The Altera UTOPIA Level 2 Slave MegaCore function is designed for 
use in PHY layer devices that transfer data to and from asynchronous 
transfer mode (ATM) devices using the standard UTOPIA bus. The 
MegaCore function comprises a separate transmitter and receiver; 
both support SPHY and MPHY operation modes. SPHY mode supports 
octet- or cell-level handshake; MPHY mode supports cell-level 
handshake.

Device families supported by the UTOPIA Level 2 Slave
Stratix II, Stratix II GX, Stratix GX, Stratix, HardCopy II, 
HardCopy Stratix, Cyclone II, and Cyclone.  


Viterbi Compiler                                            v4.4.0
--------------------------------------------------------------------
High-Speed Parallel Decoder    
Low-Speed/Hybrid Serial Decoder

The Altera Viterbi Compiler generates MegaCore functions that decode 
convolutional codes by using an asymptotically optimum decoding 
technique. In its basic form, Viterbi decoding is an efficient, 
recursive algorithm that performs an optimal exhaustive search. A 
convolutional encoder and Viterbi decoder can be used together to 
provide error correction over a noisy channel, such as a 
communications channel. A convolutional encoder adds redundancy (by 
adding extra bits) to a data stream before transmission.

Device families supported by Viterbi Compiler include Stratix II, 
Stratix II GX, Stratix GX, Stratix, HardCopy II, HardCopy Stratix, 
Cyclone II, and Cyclone.
	


Last updated April 2006
Copyright(C) 2006 Altera Corporation. All rights reserved.
