digital audio to FCDEV3B

[Serg l]

Mychaela,

I was looking into vanilla TI DSP datasheet, which should resemble the core
inside the Calypso chip here http://www.ti.com/lit/ug/spru307a/spru307a.pdf
and registers mapping document. Based on that MCSI got to be a
double-buffered SPI which would save us from the frame slips.

It is not clear if TX pins are tri-state, thanks for pointing out to this,
I just assumed that since it is SPI compliant it just got to be tri-state
outputs.

Also it could be possible to drive the whole thing in a TDM mode nicely,
when each bit from the same port is transmitted not every clock tick, but
in one of 16 positions (channels), this way I can use the same frame sync
without messing with chip select signals. This functionality seems to be
not related to the DSP application itself and configurable via control
registers, which seem to be fully mapped into ARM address space.

I understand your concerns about messing with off-the-shelf stuff, so I
will just try to play with MCSI off the C155  while you take care of
FCDEV3B :)