The original FreeCalypso project plan was to proceed directly to building a
quadband design based on the Leonardo schematics found on 52rd.com in 2011,
redoing the layout almost entirely anew based on those schematics.  This plan
has been revised in favor of a more conservative one: our first development
board will be based on a direct reuse of the known-working GTA02 modem PCB
layout from Openmoko, which necessarily includes copying Om's RF front end
which is only triband rather than quadband.

This package contains a BOM+netlist design that exactly matches Openmoko's
modem in the core and features all of the peripherals we would like to have on
our development board.

There are no graphical schematics for this board design; the design has been
captured in a text-based design entry language based on the structural subset
of Verilog instead of graphics.  The structural Verilog source files from which
the board netlist has been compiled can be found in the vsrc and vsrc_ext
subdirectories; the vsrc directory contains those modules which capture
circuits contained in the core section (the one that is a copy of Openmoko's
GTA02 modem), whereas the vsrc_ext directory contains those modules which
capture peripheral circuits added outside of that core.  The file named MCL is
the Master Component List; it lists all components on the entire board.

The current intent is that the PCB layout of our FCDEV3B board be done in PADS,
rather than any other software.  A major objective is to lift the PCB layout of
the modem section directly out of Openmoko's GTA02 board and reuse it as close
to verbatim as possible, and Openmoko's historical PCB layout is in PADS format.
I have considered developing a translator from PADS into FOSS PCB, but the task
appears to be gargantuan; as for other commercial (proprietary) CAD packages,
some can import PADS files, but practical experience shows that the translation
they perform is quite far from lossless.  Therefore, doing the layout of our
FCDEV3B board in PADS seems to be the most practical option.

Please see the Notes file for more detailed PADS import and PCB layout
instructions.

The final netlist in PADS format is pads-import-netlist.asc; *.unet are
intermediate steps from the structural Verilog sources toward that final
netlist.  The compilation steps codified in the Makefile are performed by ueda
programs written by the same author as this board design; the source code for
these programs can be downloaded here:

https://bitbucket.org/falconian/ueda-linux
