FreeCalypso > hg > ueda-linux
comparison ueda/sverp/struct.h @ 0:cd92449fdb51
initial import of ueda and ifctf-part-lib from ifctfvax CVS
| author | Space Falcon <falcon@ivan.Harhan.ORG> |
|---|---|
| date | Mon, 20 Jul 2015 00:24:37 +0000 |
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| children |
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| -1:000000000000 | 0:cd92449fdb51 |
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| 1 /* | |
| 2 * Data structures for our structural Verilog to flat netlist processor | |
| 3 */ | |
| 4 | |
| 5 /* | |
| 6 * Definition of a module as a thing in itself, before elaboration | |
| 7 */ | |
| 8 struct module_def { | |
| 9 char *name; | |
| 10 struct module_def *next; | |
| 11 int is_primitive; | |
| 12 /* ports and internal nets */ | |
| 13 struct module_net_def *nets; | |
| 14 int nports; | |
| 15 /* counts of individual wires (buses expanded) */ | |
| 16 int nwires_ports; | |
| 17 int nwires_internal; | |
| 18 /* downward instantiations */ | |
| 19 struct module_def_subinst *subinst; | |
| 20 /* primitives only */ | |
| 21 int prim_numeric_pins; | |
| 22 int prim_is_mapped; | |
| 23 }; | |
| 24 | |
| 25 /* | |
| 26 * Definition of a wire or bus visible in a module (thing-in-itself), | |
| 27 * either port or internal wire. | |
| 28 */ | |
| 29 struct module_net_def { | |
| 30 char *name; | |
| 31 struct module_net_def *next; | |
| 32 int is_port; | |
| 33 int def_complete; | |
| 34 int is_bus; | |
| 35 int bus_msb; | |
| 36 int bus_lsb; | |
| 37 int bus_width; | |
| 38 int array_index; | |
| 39 }; | |
| 40 | |
| 41 /* | |
| 42 * Definition of an instantiation statement in a module as a thing-in-itself | |
| 43 */ | |
| 44 struct module_def_subinst { | |
| 45 char *submod_name; | |
| 46 struct module_def *submod_def; | |
| 47 char *inst_name; | |
| 48 struct module_def_subinst *next; | |
| 49 struct connect_entry *connections; | |
| 50 int connect_by_order; | |
| 51 }; | |
| 52 | |
| 53 /* | |
| 54 * Definition of a connection from a module to a downward port | |
| 55 */ | |
| 56 struct connect_entry { | |
| 57 struct connect_entry *next; | |
| 58 /* upper end of the connection */ | |
| 59 struct module_net_def *up_netdef; /* NULL means no connect */ | |
| 60 int up_offset; | |
| 61 int up_width; | |
| 62 /* lower end of the connection before link pass */ | |
| 63 char *down_portname; /* NULL means connect by order */ | |
| 64 int down_range_given; | |
| 65 int down_range_msb; | |
| 66 int down_range_lsb; | |
| 67 /* lower end of the connection after link pass */ | |
| 68 struct module_net_def *down_portdef; | |
| 69 int down_offset; | |
| 70 int down_width; | |
| 71 /* source line number */ | |
| 72 int src_lineno; | |
| 73 }; | |
| 74 | |
| 75 /* output of the elaboration pass */ | |
| 76 | |
| 77 struct output_net { | |
| 78 char *name; /* NULL means no connect */ | |
| 79 int npoints; /* # of package pins connected to this net */ | |
| 80 struct output_net *next; | |
| 81 /* no-connect pseudo-nets */ | |
| 82 char *nc_module_name; | |
| 83 int nc_module_lineno; | |
| 84 char *nc_module_inst; | |
| 85 }; | |
| 86 | |
| 87 struct output_element { | |
| 88 struct module_def *prim_def; | |
| 89 char *hier_inst_name; | |
| 90 struct output_net **connections; | |
| 91 struct output_element *next; | |
| 92 }; |
