# HG changeset patch # User Space Falcon # Date 1441582427 0 # Node ID 89f63833708eaa0e1bb27f0dd1a3e58f47f90603 # Parent be8bbcbf2163d72c21445611e83aac577967d853 RVT memory size drastically increased, now almost no loss with ext LCD out diff -r be8bbcbf2163 -r 89f63833708e chipsetsw/riviera/rvt/rvt_pool_size.h --- a/chipsetsw/riviera/rvt/rvt_pool_size.h Sun Sep 06 08:38:36 2015 +0000 +++ b/chipsetsw/riviera/rvt/rvt_pool_size.h Sun Sep 06 23:33:47 2015 +0000 @@ -37,10 +37,8 @@ #if (TEST==1) #define TRACE_MB1_SIZE (750000) /*(25000)*/ -#elif defined(RVM_R2D_SWE) /* FreeCalypso external LCD output */ - #define TRACE_MB1_SIZE (150000) #elif (!GSMLITE) - #define TRACE_MB1_SIZE (25000) + #define TRACE_MB1_SIZE (400000) /* For FreeCalypso external LCD out */ #else #define TRACE_MB1_SIZE (4000) #endif diff -r be8bbcbf2163 -r 89f63833708e chipsetsw/system/template/gsm_ds_k5a3281_2092.template --- a/chipsetsw/system/template/gsm_ds_k5a3281_2092.template Sun Sep 06 08:38:36 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,206 +0,0 @@ -/* - * Integrated Protocol Stack Linker command file (all components) - * - * Target : ARM - * - * Copyright (c) Texas Instruments 2002, Condat 2002 - * - * This version of the linker script template has been concocted - * by Spacefalcon the Outlaw, based on gsm_ds_amd8_lj3.template, - * in order to build the GSM firmware for the memory configuration - * found in the Openmoko GTA0x GSM modem, which consists of the - * K5A3281 flash+RAM MCP plus the 512 KiB of internal RAM in the - * Calypso (PD751992A) chip itself. - */ - --c /* Autoinitialize variables at runtime */ - -/*********************************/ -/* SPECIFY THE SYSTEM MEMORY MAP */ -/*********************************/ - -MEMORY -{ - /* CS0: Flash 4 Mbytes ****************************************************/ - /* Interrupt Vectors Table */ - I_MEM (RXI) : org = 0x00000000 len = 0x00000100 - - /* Boot Sector */ - B_MEM (RXI) : org = 0x00000100 len = 0x00001f00 - - /* Magic Word for Calypso Boot ROM */ - MWC_MEM (RXI) : org = 0x00002000 len = 0x00000004 fill = 0x0000001 - - /* Program Memory */ - P_MEM1 (RXI) : org = 0x00004000 len = 0x00000700 - P_MEM2 (RXI) : org = 0x00004700 len = 0x00000004 - P_MEM3 (RXI) : org = 0x00004704 len = 0x0037b8fc - - /* FFS Area */ - FFS_MEM (RX) : org = 0x00380000 len = 0x00080000 - /**************************************************************************/ - - /* CS1: External SRAM 1 Mbytes ********************************************/ - /* Data Memory */ - - /* - *** HACK by Spacefalcon the Outlaw *** - * - * The starting Leonardo version (gsm_ds_amd8_lj3.template) had two - * external SRAM regions: D_MEM1 and D_MEM2. When I tried removing - * D_MEM2 and keeping only D_MEM1, the linker started behaving oddly - * in that the sections were emitted in the wrong order, and the - * addresses printed in the map file were bogus. The resulting m0 - * images seemed to still work correctly, but I feel that having the - * linker act "correctly" is better. - * - * My current hack-solution is to split the 1 MiB physical XRAM - * into D_MEM1 and D_MEM2 of 512 KiB each. As it happens, the total - * XRAM usage of the current firmware is a little below 512 KiB anyway. - */ - - D_MEM1 (RW) : org = 0x01000000 len = 0x000C0000 - D_MEM2 (RW) : org = 0x010C0000 len = 0x00040000 - /**************************************************************************/ - - /* CS6: Calypso Internal SRAM 512 kbytes **********************************/ - /* Code & Variables Memory */ - S_MEM (RXW) : org = 0x00800000 len = 0x00080000 - /**************************************************************************/ -} - -/***********************************************/ -/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */ -/***********************************************/ - -/* - * Since the bootloader directly calls the INT_Initialize() routine located - * in int.s, this int.s code must always be mapped at the same address - * (usually in the second flash sector). Its length is about 0x500 bytes. - * Then comes the code that need to be loaded into the internal RAM. - */ - -SECTIONS -{ - .intvecs : {} > I_MEM /* Interrupt Vectors Table */ - .monitor : > B_MEM /* Monitor Constants & Code */ - { - $(CONST_BOOT_LIB) - } - - .inttext : {} > P_MEM1 /* int.s Code */ - - .bss_dar : > D_MEM1 /* DAR SWE Variables */ - { - $(BSS_DAR_LIB) - } - - /* - * The .bss section should not be split to ensure it is initialized to 0 - * each time the SW is reset. So the whole .bss is mapped either in D_MEM1 - * or in D_MEM2. - * - * Falcon's note for K5A3281: see the comments above where the memory - * regions are defined. - */ - - .bss : > D_MEM1 | D_MEM2 /* Global & Static Variables */ - { - $(BSS_BOOT_LIB) - } - - /* - * All .bss sections, which must be mapped in internal RAM must be - * grouped in order to initialized the corresponding memory to 0. - * This initialization is done in int.s file before calling the Nucleus - * routine. - */ - - GROUP - { - S_D_Mem /* Label of start address of .bss section in Int. RAM */ - .DintMem - { - - /* - * .bss sections of the application - */ - - $(BSS_LIBS) - - } - - API_HISR_stack : {} - - E_D_Mem /* Label of end address of .bss section in Int. RAM */ - } > S_MEM - - /* - * .text and .const sections which must be mapped in internal RAM. - */ - - .ldfl : {} > P_MEM2 /* Used to know the start load address */ - GROUP load = P_MEM3, run = S_MEM - { - S_P_Mem /* Label of start address of .text & .const sections in Int. RAM */ - .PIntMem - { - /* - * .text and .const sections of the application. - * - * The .veneer sections correspond exactly to .text:v&n sections - * implementing the veneer functions. The .text:v$n -> .veneer - * translation is performed by PTOOL software when PTOOL_OPTIONS - * environement variable is set to veneer_section. - */ - - $(CONST_LIBS) - - } - E_P_Mem /* Label of end address of .text and .const sections in Int. RAM */ - } - - /* - * The rest of the code is mapped in flash, however the trampolines - * load address should be consistent with .text. - */ - COMMENT2START - `trampolines load = P_MEM3, run = S_MEM - COMMENT2END - - .text : {} > P_MEM3 /* Code */ - - /* - * The rest of the constants is mapped in flash. - * The .cinit section should not be split. - */ - - .cinit : {} > P_MEM3 /* Initialization Tables */ - .const : {} > P_MEM3 /* Constant Data */ - KadaAPI : {} > P_MEM3 /* ROMized CLDC */ - - .javastack: {} >> D_MEM1 | D_MEM2 /* Java stack */ - - .stackandheap : > D_MEM1 /* System Stacks, etc... */ - { - /* Leave 20 32bit words for register pushes. */ - . = align(8); - . += 20 * 4; - - /* Stack for abort and/or undefined modes. */ - exception_stack = .; - - /* Leave 38 32bit words for state saving on exceptions. */ - _xdump_buffer = .; - . += 38 * 4; - . = align(8); - - /* Beginning of stacks and heap area - 2.75 kbytes (int.s) */ - stack_segment = .; - . += 0xB00; - } - - .data : {} > D_MEM1 /* Initialized Data */ - .sysmem : {} > D_MEM1 /* Dynamic Memory Allocation Area */ - -} diff -r be8bbcbf2163 -r 89f63833708e chipsetsw/system/template/gsm_ds_k5a3281_big.template --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/chipsetsw/system/template/gsm_ds_k5a3281_big.template Sun Sep 06 23:33:47 2015 +0000 @@ -0,0 +1,218 @@ +/* + * Integrated Protocol Stack Linker command file (all components) + * + * Target : ARM + * + * Copyright (c) Texas Instruments 2002, Condat 2002 + * + * This version of the linker script template has been concocted + * by Spacefalcon the Outlaw, based on gsm_ds_amd8_lj3.template, + * in order to build the GSM firmware for the memory configuration + * found in the Openmoko GTA0x GSM modem, which consists of the + * K5A3281 flash+RAM MCP plus the 512 KiB of internal RAM in the + * Calypso (PD751992A) chip itself. + * + * More recent revision: the present version has been concocted in order to + * squeeze TI's pdt_2092 configuration (on-board UI enabled) into the same + * small physical memory config, with the additional complication that we need + * a lot of RAM for our enlargement of RVT's memory bank which is in turn + * needed for our external LCD output hack. We will probably have to use + * this linker script version for pdt_2091 built in this tree as well, + * as it's too difficult to conditionalize the RVT enlargement on pdt_2092. + */ + +-c /* Autoinitialize variables at runtime */ + +/*********************************/ +/* SPECIFY THE SYSTEM MEMORY MAP */ +/*********************************/ + +MEMORY +{ + /* CS0: Flash 4 Mbytes ****************************************************/ + /* Interrupt Vectors Table */ + I_MEM (RXI) : org = 0x00000000 len = 0x00000100 + + /* Boot Sector */ + B_MEM (RXI) : org = 0x00000100 len = 0x00001f00 + + /* Magic Word for Calypso Boot ROM */ + MWC_MEM (RXI) : org = 0x00002000 len = 0x00000004 fill = 0x0000001 + + /* Program Memory */ + P_MEM1 (RXI) : org = 0x00004000 len = 0x00000700 + P_MEM2 (RXI) : org = 0x00004700 len = 0x00000004 + P_MEM3 (RXI) : org = 0x00004704 len = 0x0037b8fc + + /* FFS Area */ + FFS_MEM (RX) : org = 0x00380000 len = 0x00080000 + /**************************************************************************/ + + /* CS1: External SRAM 1 Mbytes ********************************************/ + /* Data Memory */ + + /* + *** HACK by Spacefalcon the Outlaw *** + * + * The starting Leonardo version (gsm_ds_amd8_lj3.template) had two + * external SRAM regions: D_MEM1 and D_MEM2. When I tried removing + * D_MEM2 and keeping only D_MEM1, the linker started behaving oddly + * in that the sections were emitted in the wrong order, and the + * addresses printed in the map file were bogus. The resulting m0 + * images seemed to still work correctly, but I feel that having the + * linker act "correctly" is better. + * + * My original hack-solution was to split the 1 MiB physical XRAM + * into D_MEM1 and D_MEM2 of 512 KiB each. As it happens, the total + * XRAM usage of the standard pdt_2091 firmware is a little below + * 512 KiB anyway. + * + * Revision for pdt_2092 memory usage: D_MEM2 is now the last 64 KiB + * and D_MEM1 is the rest. + */ + + D_MEM1 (RW) : org = 0x01000000 len = 0x000F0000 + D_MEM2 (RW) : org = 0x010F0000 len = 0x00010000 + /**************************************************************************/ + + /* CS6: Calypso Internal SRAM 512 kbytes **********************************/ + /* Code & Variables Memory */ + S_MEM (RXW) : org = 0x00800000 len = 0x00080000 + /**************************************************************************/ +} + +/***********************************************/ +/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */ +/***********************************************/ + +/* + * Since the bootloader directly calls the INT_Initialize() routine located + * in int.s, this int.s code must always be mapped at the same address + * (usually in the second flash sector). Its length is about 0x500 bytes. + * Then comes the code that need to be loaded into the internal RAM. + */ + +SECTIONS +{ + .intvecs : {} > I_MEM /* Interrupt Vectors Table */ + .monitor : > B_MEM /* Monitor Constants & Code */ + { + $(CONST_BOOT_LIB) + } + + .inttext : {} > P_MEM1 /* int.s Code */ + + .bss_dar : > D_MEM1 /* DAR SWE Variables */ + { + $(BSS_DAR_LIB) + } + + /* + * The .bss section should not be split to ensure it is initialized to 0 + * each time the SW is reset. So the whole .bss is mapped either in D_MEM1 + * or in D_MEM2. + * + * Falcon's note for K5A3281: see the comments above where the memory + * regions are defined. + */ + + .bss : > D_MEM1 | D_MEM2 /* Global & Static Variables */ + { + $(BSS_BOOT_LIB) + } + + /* + * All .bss sections, which must be mapped in internal RAM must be + * grouped in order to initialized the corresponding memory to 0. + * This initialization is done in int.s file before calling the Nucleus + * routine. + */ + + GROUP + { + S_D_Mem /* Label of start address of .bss section in Int. RAM */ + .DintMem + { + + /* + * .bss sections of the application + */ + + $(BSS_LIBS) + + } + + API_HISR_stack : {} + + E_D_Mem /* Label of end address of .bss section in Int. RAM */ + } > S_MEM + + /* + * .text and .const sections which must be mapped in internal RAM. + */ + + .ldfl : {} > P_MEM2 /* Used to know the start load address */ + GROUP load = P_MEM3, run = S_MEM + { + S_P_Mem /* Label of start address of .text & .const sections in Int. RAM */ + .PIntMem + { + /* + * .text and .const sections of the application. + * + * The .veneer sections correspond exactly to .text:v&n sections + * implementing the veneer functions. The .text:v$n -> .veneer + * translation is performed by PTOOL software when PTOOL_OPTIONS + * environement variable is set to veneer_section. + */ + + $(CONST_LIBS) + + } + E_P_Mem /* Label of end address of .text and .const sections in Int. RAM */ + } + + /* + * The rest of the code is mapped in flash, however the trampolines + * load address should be consistent with .text. + */ + COMMENT2START + `trampolines load = P_MEM3, run = S_MEM + COMMENT2END + + .text : {} > P_MEM3 /* Code */ + + /* + * The rest of the constants is mapped in flash. + * The .cinit section should not be split. + */ + + .cinit : {} > P_MEM3 /* Initialization Tables */ + .const : {} > P_MEM3 /* Constant Data */ + KadaAPI : {} > P_MEM3 /* ROMized CLDC */ + + .javastack: {} >> D_MEM1 | D_MEM2 /* Java stack */ + + .stackandheap : > D_MEM1 /* System Stacks, etc... */ + { + /* Leave 20 32bit words for register pushes. */ + . = align(8); + . += 20 * 4; + + /* Stack for abort and/or undefined modes. */ + exception_stack = .; + + /* Leave 38 32bit words for state saving on exceptions. */ + _xdump_buffer = .; + . += 38 * 4; + . = align(8); + + /* Beginning of stacks and heap area - 2.75 kbytes (int.s) */ + stack_segment = .; + . += 0xB00; + } + + .data : {} > D_MEM1 /* Initialized Data */ + .sysmem : {} > D_MEM1 /* Dynamic Memory Allocation Area */ + +} diff -r be8bbcbf2163 -r 89f63833708e g23m/pdt_2092.mak --- a/g23m/pdt_2092.mak Sun Sep 06 08:38:36 2015 +0000 +++ b/g23m/pdt_2092.mak Sun Sep 06 23:33:47 2015 +0000 @@ -1945,7 +1945,7 @@ ../chipsetsw/system/Main/sys_dummy.c \ ../chipsetsw/system/Main/mem_load.c \ ../chipsetsw/system/Main/int.s \ - ../chipsetsw/system/template/gsm_ds_k5a3281_2092.template \ + ../chipsetsw/system/template/gsm_ds_k5a3281_big.template \ __out__/gsm_mf_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/bootloader.lib \ __out__/gsm_mf_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/tpudrv.lib \ __out__/gsm_mf_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/l1_int.lib \ @@ -47726,7 +47726,7 @@ # exec.: perl system/busyb/tools/make_cmd.pl # # SOURCES: -# ../chipsetsw/system/template/gsm_ds_k5a3281_2092.template +# ../chipsetsw/system/template/gsm_ds_k5a3281_big.template # __out__/gsm_mf_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/bootloader.lib # __out__/gsm_mf_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/tpudrv.lib # __out__/gsm_mf_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/l1_int.lib @@ -47751,7 +47751,7 @@ # RULES: __out__/gsm_mf_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/lnk__mf_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0.cmd: \ - ../chipsetsw/system/template/gsm_ds_k5a3281_2092.template \ + ../chipsetsw/system/template/gsm_ds_k5a3281_big.template \ __out__/gsm_mf_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/bootloader.lib \ __out__/gsm_mf_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/tpudrv.lib \ __out__/gsm_mf_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/l1_int.lib \