# HG changeset patch # User Space Falcon # Date 1441675014 0 # Node ID 176f5b1bc3604c5927f11e4d3a28b54a17c84fd7 # Parent 1a81baea22d718f6d96e06e0eb029e209e037620 first round of changes for the Pirelli diff -r 1a81baea22d7 -r 176f5b1bc360 chipsetsw/drivers/drv_app/ffs/board/dev.c --- a/chipsetsw/drivers/drv_app/ffs/board/dev.c Mon Sep 07 19:26:24 2015 +0000 +++ b/chipsetsw/drivers/drv_app/ffs/board/dev.c Tue Sep 08 01:16:54 2015 +0000 @@ -88,6 +88,42 @@ // Note that does NOT support a flash definition with different sized blocks // so all blocks contained in the device definition MUST be the same size! +// 256 KiB sectors +static const struct block_info_s flash_32x256[] = +{ + { 0x000000, 18 }, + { 0x040000, 18 }, + { 0x080000, 18 }, + { 0x0C0000, 18 }, + { 0x100000, 18 }, + { 0x140000, 18 }, + { 0x180000, 18 }, + { 0x1C0000, 18 }, + { 0x200000, 18 }, + { 0x240000, 18 }, + { 0x280000, 18 }, + { 0x2C0000, 18 }, + { 0x300000, 18 }, + { 0x340000, 18 }, + { 0x380000, 18 }, + { 0x3C0000, 18 }, + { 0x400000, 18 }, + { 0x440000, 18 }, + { 0x480000, 18 }, + { 0x4C0000, 18 }, + { 0x500000, 18 }, + { 0x540000, 18 }, + { 0x580000, 18 }, + { 0x5C0000, 18 }, + { 0x600000, 18 }, + { 0x640000, 18 }, + { 0x680000, 18 }, + { 0x6C0000, 18 }, + { 0x700000, 18 }, + { 0x740000, 18 }, + { 0x780000, 18 }, + { 0x7C0000, 18 } +}; // 128x64kb static const struct block_info_s flash_128x64[] = @@ -316,10 +352,11 @@ /********** AMD Devices ***********************************************/ - // AMD Am29DL640F. Ignoring the 8kB sectors + // Spansion S71PL129NC0 used in Pirelli DP-L10 // Multi-id device: 0x227E, 0x2221, 0x2200. Converted to 0x2100 - { &flash_16x64[0], (char *) 0x01800000, MANUFACT_AMD, 0x2100, - FFS_DRIVER_AMD, 15 }, + // This is an aftermarket FFS config for the Pirelli target + { &flash_32x256[0], (char *) 0x02480000, MANUFACT_AMD, 0x2100, + FFS_DRIVER_AMD, 6 }, // AMD Am29DL640G. Ignoring the 8kB sectors // Multi-id device: 0x227E, 0x2202, 0x2201. Converted to 0x0201 diff -r 1a81baea22d7 -r 176f5b1bc360 chipsetsw/drivers/drv_app/uart/uartfax.c --- a/chipsetsw/drivers/drv_app/uart/uartfax.c Mon Sep 07 19:26:24 2015 +0000 +++ b/chipsetsw/drivers/drv_app/uart/uartfax.c Tue Sep 08 01:16:54 2015 +0000 @@ -553,7 +553,7 @@ SYS_UWORD8 rts_level; /* RTS on RS232 side, CTS on chipset side. 1: The RS232 line is deactivated (low). */ -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) SYS_UWORD8 dtr_level; /* Controlled with an I/O on C & D-Sample and handled by Calypso+ on E-Sample. 1: The RS232 line is deactivated (low). */ @@ -915,7 +915,7 @@ * lose events detected in the RX interrupt handler. */ -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) if (call_source == 3) /* Call from Rx HISR */ dtr_level = uart->dtr_level_saved[uart->index_hisr]; else @@ -932,7 +932,7 @@ state |= ((((SYS_UWORD32) uart->rts_level) << RTS) | -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) (((SYS_UWORD32) dtr_level) << DTR) | #endif @@ -955,7 +955,7 @@ * DTR is supported on C, D & E-Sample. */ -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) state |= (((SYS_UWORD32) uart->dtr_level) << SA); #endif @@ -1965,7 +1965,7 @@ SER_restart_uart_sleep_timer (); uart_sleep_timer_enabled = 1; -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) uart->index_hisr = (uart->index_hisr + 1) & 0x01; /* 0 or 1 */ #endif @@ -2166,7 +2166,7 @@ (uart->rd_call_setup == rm_reInstall))) { if ((bytes_in_rx_buffer >= uart->rx_threshold_level) || -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) uart->dtr_change_detected[uart->index_hisr] || #endif uart->break_received || @@ -2179,7 +2179,7 @@ uart->reading_suspended = 0; uart->break_received = 0; uart->esc_seq_received = 0; -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) uart->dtr_change_detected[uart->index_hisr] = 0; #endif } @@ -2592,7 +2592,7 @@ else { uart->tx_stopped_by_driver = 0; - LowGPIO(1); + /* LowGPIO(1); */ #if ((CHIPSET != 5) && (CHIPSET != 6)) /* @@ -2999,7 +2999,7 @@ else uart->rts_level = 1; -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) /* * On C & D-Sample, 2 I/O are used to control DCD and DTR on UART Modem. * DCD: I/O 2 (output) @@ -3219,7 +3219,7 @@ WRITE_UART_REGISTER (uart, IER, 0x00); -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) AI_MaskIT (ARMIO_MASKIT_GPIO); #elif (CHIPSET == 12) DISABLE_DSR_INTERRUPT (uart); @@ -3360,7 +3360,7 @@ else uart->rts_level = 1; -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) /* * Read the state of DTR and select the edge. */ @@ -4322,8 +4322,10 @@ /* If we have been stopped due to high RTS, we have to * wake up application processor by IRQ via IO1 -HW */ +#if 0 if (uart->tx_stopped_by_driver) HighGPIO(1); +#endif /* * If: @@ -4544,7 +4546,7 @@ *state |= ((((SYS_UWORD32) uart->rts_level) << RTS) | -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) (((SYS_UWORD32) uart->dtr_level) << DTR) | #endif @@ -4568,7 +4570,7 @@ * DTR is supported on C, D & E-Sample. */ -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) *state |= (((SYS_UWORD32) uart->dtr_level) << SA); #endif @@ -4639,7 +4641,7 @@ * DSR is not supported on all platforms. */ -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) if (mask & (1 << SA)) #else if ((mask & (1 << SA)) || (mask & (1 << DCD))) @@ -4741,7 +4743,7 @@ * The DCD field is ignored if the SB bit of the mask is set. */ -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) if (!(mask & (1 << SB)) && (mask & (1 << DCD))) { @@ -4777,7 +4779,7 @@ * DCD is supported on C, D & E-Sample. */ -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) if (mask & (1 << SB)) { @@ -4883,7 +4885,7 @@ case RX_DATA: -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) uart->index_it = (uart->index_it + 1) & 0x01; /* 0 or 1 */ uart->dtr_change_detected[uart->index_it] = 0; uart->dtr_level_saved[uart->index_it] = uart->dtr_level; @@ -5017,7 +5019,7 @@ return (result); } -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) /******************************************************************************* * * UAF_DTRInterruptHandler diff -r 1a81baea22d7 -r 176f5b1bc360 chipsetsw/drivers/drv_core/armio/armio.c --- a/chipsetsw/drivers/drv_core/armio/armio.c Mon Sep 07 19:26:24 2015 +0000 +++ b/chipsetsw/drivers/drv_core/armio/armio.c Tue Sep 08 01:16:54 2015 +0000 @@ -233,32 +233,31 @@ // CLKM_IO_CNTL register configuration : // select IOs 6,8,9,10,11,12 and 13 on the pins instead of MCSI and MCUEN signals. - #if (CHIPSET != 12) + + // Modified for Pirelli DP-L10 in this version + + AI_EnableBit(0); + AI_EnableBit(1); AI_EnableBit(2); + AI_EnableBit(3); AI_EnableBit(4); - #endif /* Bits 5,6,7,8 are used to output I/O 9,10,11,12 or MCSI pins */ /* If Bluetooth, IO should be disabled, outputting MCSI used for Bluetooth voice */ -#ifdef BTEMOBILE - #if (CHIPSET != 12) + /* MCSI is enabled on the Pirelli */ +#if 1 AI_DisableBit(5); AI_DisableBit(6); AI_DisableBit(7); AI_DisableBit(8); - #endif #else - #if (CHIPSET != 12) AI_EnableBit(5); AI_EnableBit(6); AI_EnableBit(7); AI_EnableBit(8); #endif -#endif - #if (CHIPSET != 12) AI_EnableBit(9); - #endif // ARMIO_OUT register configuration : // set IOs 8,9,10,11,12 and 13 as high @@ -281,30 +280,14 @@ // set IOs 1 and 8 to 13 as high // set IOs 0 and 2 to 7 as low // On D-Sample GPIO 1 must be set to high to enable the audio amplifier. - #if (OP_L1_STANDALONE == 0) -// CC test -#if 1 // Dmitriy: GPIO 1 is the interrupt for the ext host, set it to 0 - *((volatile SYS_UWORD16 *) ARMIO_OUT) = 0x3F00; -#else - *((volatile SYS_UWORD16 *) ARMIO_OUT) = 0x3F02; -#endif - //*((volatile SYS_UWORD16 *) ARMIO_OUT) = 0x3F01; -// end - #else - *((volatile SYS_UWORD16 *) ARMIO_OUT) = 0x3F01; - #endif + + // Modified for Pirelli DP-L10 in this version - // ARMIO_CNTL_REG register configuration : - // set IOs 1,2,5,7,9,14 and 15 as ouputs. -// CC test 0316 + *((volatile SYS_UWORD16 *) ARMIO_OUT) = 0x0000; + AI_ConfigBitAsOutput(1); -// end - AI_ConfigBitAsOutput(2); - AI_ConfigBitAsOutput(5); + AI_ConfigBitAsOutput(4); AI_ConfigBitAsOutput(7); - AI_ConfigBitAsOutput(9); - AI_ConfigBitAsOutput(14); - AI_ConfigBitAsOutput(15); #endif } diff -r 1a81baea22d7 -r 176f5b1bc360 chipsetsw/layer1/tpu_drivers/source0/tpudrv12.h --- a/chipsetsw/layer1/tpu_drivers/source0/tpudrv12.h Mon Sep 07 19:26:24 2015 +0000 +++ b/chipsetsw/layer1/tpu_drivers/source0/tpudrv12.h Tue Sep 08 01:16:54 2015 +0000 @@ -16,7 +16,7 @@ #include "rf.cfg" -#define CONFIG_TARGET_GTAMODEM 1 +#define CONFIG_TARGET_PIRELLI 1 //--- RITA PG declaration