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date Mon, 01 Jun 2015 03:24:05 +0000
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1 ;******************************************************************************
2 ; TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
3 ;
4 ; Property of Texas Instruments -- For Unrestricted Internal Use Only
5 ; Unauthorized reproduction and/or distribution is strictly prohibited. This
6 ; product is protected under copyright law and trade secret law as an
7 ; unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All
8 ; rights reserved.
9 ;
10 ;
11 ; Filename : int.s
12 ;
13 ; Description : Nucleus initialization
14 ;
15 ; Project : Drivers
16 ;
17 ; Author : proussel@ti.com Patrick Roussel.
18 ;
19 ; Version number : 1.3
20 ;
21 ; Date and time : 07/23/98 15:36:07
22 ;
23 ; Previous delta : 07/23/98 15:36:06
24 ;
25 ; SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release1.5/mod/emu/EMU_MCMP/eva3_drivers/source/SCCS/s.int.s
26 ;
27 ; Sccs Id (SID) : '@(#) int.s 1.3 07/23/98 15:36:07 '
28 ;/*************************************************************************/
29 ;/* */
30 ;/* Copyright (c) 1993 - 1996 Accelerated Technology, Inc. */
31 ;/* */
32 ;/* PROPRIETARY RIGHTS of Accelerated Technology are involved in the */
33 ;/* subject matter of this material. All manufacturing, reproduction, */
34 ;/* use, and sales rights pertaining to this subject matter are governed */
35 ;/* by the license agreement. The recipient of this software implicitly */
36 ;/* accepts the terms of the license. */
37 ;/* */
38 ;/*************************************************************************/
39 ;
40 ;/*************************************************************************/
41 ;/* */
42 ;/* FILE NAME VERSION */
43 ;/* */
44 ;/* int.s PLUS/THUMB/T 1.3 */
45 ;/* */
46 ;/* COMPONENT */
47 ;/* */
48 ;/* IN - Initialization */
49 ;/* */
50 ;/* DESCRIPTION */
51 ;/* */
52 ;/* This file contains the target processor dependent initialization */
53 ;/* routines and data. */
54 ;/* */
55 ;/* AUTHOR */
56 ;/* */
57 ;/* Barry Sellew, Accelerated Technology, Inc. */
58 ;/* */
59 ;/* DATA STRUCTURES */
60 ;/* */
61 ;/* INT_Vectors Interrupt vector table */
62 ;/* */
63 ;/* FUNCTIONS */
64 ;/* */
65 ;/* INT_Initialize Target initialization */
66 ;/* INT_Vectors_Loaded Returns a NU_TRUE if all the */
67 ;/* default vectors are loaded */
68 ;/* INT_Setup_Vector Sets up an actual vector */
69 ;/* */
70 ;/* DEPENDENCIES */
71 ;/* */
72 ;/* nucleus.h System constants */
73 ;/* */
74 ;/* HISTORY */
75 ;/* */
76 ;/* NAME DATE REMARKS */
77 ;/* */
78 ;/* B. Sellew 01-19-1996 Created initial version 1.0 */
79 ;/* B. Sellew 01-22-1996 Verified version 1.0 */
80 ;/* B. Sellew 03-14-1996 Modified to use the ROM */
81 ;/* initialization method, */
82 ;/* resulting in version 1.1 */
83 ;/* B. Sellew 03-14-1996 Verified version 1.1 */
84 ;/* B. Sellew 02-06-1997 Created version 1.3 */
85 ;/* B. Sellew 02-06-1997 Verified version 1.3 */
86 ;/* M. Manning 06-02-1997 Added support for FIQ */
87 ;/* interrupts. Bumped to 1.4 */
88 ;/* M. Manning 06-03-1997 Verified version 1.4 */
89 ;/* */
90 ;/*************************************************************************/
91 ;#define NU_SOURCE_FILE
92 ;
93 ;#include "nucleus.h" /* System constants */
94 ;
95 ;
96 ;/* Define constants used in low-level initialization. */
97 ;
98 ;
99
100
101 .if LONG_JUMP >= 3
102 .global IND_CALL
103 .global _f_load_int_mem
104 .global _ResetVector
105
106 ; Initialization for variable S_D_Mem
107 .sect ".cinit"
108 .align 4
109
110 ; S_D_Mem is a UWORD32, See mem_load.c
111 ;
112 .field 4,32
113 .field _S_D_Mem+0,32
114 .field 0,32 ; _S_D_Mem @ 0
115
116 .sect ".text"
117 .global _S_D_Mem
118 _S_D_Mem: .usect "S_D_Mem",4,4
119 .sym _S_D_Mem,_S_D_Mem,14,2,32 ; For debug only
120
121
122 ; Initialization for variable E_D_Mem
123
124 .sect ".cinit"
125 .align 4
126
127
128 ; E_D_Mem is a UWORD32, See mem_load.c
129 ;
130 .field 4,32
131 .field _E_D_Mem+0,32
132 .field 0,32 ; _E_D_Mem @ 0
133
134 .sect ".text"
135 .global _E_D_Mem
136 _E_D_Mem: .usect "E_D_Mem",4,4
137 .sym _E_D_Mem,_E_D_Mem,14,2,32 ; For debug only
138
139 .endif ; (LONG_JUMP >= 3)
140
141 .if CHIPSET == 12
142 .global _f_load_int_mem
143 .global _ResetVector
144 .global _ResetVectorTestMode ; CALYPSO PLUS TEST MODE - TO BE ERASED
145 .endif
146
147 LOCKOUT .equ 00C0h ; Interrupt lockout value
148 LOCK_MSK .equ 00C0h ; Interrupt lockout mask value
149 MODE_MASK .equ 001Fh ; Processor Mode Mask
150 SUP_MODE .equ 0013h ; Supervisor Mode (SVC)
151 IRQ_MODE .equ 0012h ; Interrupt Mode (IRQ)
152 FIQ_MODE .equ 0011h ; Fast Interrupt Mode (FIQ)
153 ABORT_MODE .equ 0017h ; Abort Interrupt Mode
154 UNDEF_MODE .equ 001Bh ; Undefined Interrupt Mode (should not happen)
155
156 IRQ_STACK_SIZE .equ 128 ; Number of bytes in IRQ stack (must be align(8))
157 ; Note that the IRQ interrupt,
158 ; by default, is managed by
159 ; Nucleus PLUS. Only several
160 ; words are actually used. The
161 ; system stack is what will
162 ; actually be used for Nuclues
163 ; PLUS managed IRQ interrupts.
164 FIQ_STACK_SIZE .equ 512 ; Number of bytes in FIQ stack. (must be align(8))
165 ; This value is application
166 ; specific. By default, Nucleus
167 ; does not manage FIQ interrupts
168 ; and furthermore, leaves them
169 ; enabled virtually all the time.
170 SYSTEM_SIZE .equ 1024 ; Define the system stack size (must be align(8))
171 TIMER_SIZE .equ 1024 ; Define timer HISR stack size (must be align(8))
172 TIMER_PRIORITY .equ 2 ; Timer HISR priority (values from
173
174 .if BOARD = 34
175 ; Name value offset type W/E W/S D/Cycles
176 CS0_CONFIG .short 0x044F ; 0 Flash 32 N F 2
177 CS1_CONFIG .short 0x02CF ; 2 RAM 32 Y F 1
178 CS2_CONFIG .short 0x02CF ; 4
179 CS3_CONFIG .short 0x02CF ; 6
180 CS7_CONFIG .short 0x02C0 ; 8 Int-RAM 32 Y 0 1
181 CS5_CONFIG .short 0x02CF ; A
182 CS6_CONFIG .short 0x02C0 ; C Int-RAM 32 Y 0 1
183 RHEA_CONFIG .short 0x002A ; E ARM -> RHEA/API adaptation
184 NUM_CS_REGS .equ 8 ; number of Chip Select Config regs to program
185 .endif
186 ; 0 to 2, where 0 is highest)
187
188 ;
189 ;/* End of low-level initialization constants. */
190 ;
191 ;
192 ;/* Define the initialization flag that indicates whether or not all of the
193 ; default vectors have been loaded during initialization. */
194 ;
195 ;INT INT_Loaded_Flag;
196
197 .def _INT_Loaded_Flag
198 .bss _INT_Loaded_Flag, 4, 4
199 ;
200 ;/* Define the vector table */
201 ;
202
203 .if CHIPSET = 12
204 .sect ".start"
205
206 .ref _INT_Bootloader_Start
207
208 _ResetVector:
209 B _INT_Bootloader_Start
210
211 .sect ".indint"
212
213 .def _IndirectVectorTable
214 _IndirectVectorTable:
215 LDR PC, [PC, #0x14]
216 LDR PC, [PC, #0x14]
217 LDR PC, [PC, #0x14]
218 LDR PC, [PC, #0x14]
219 LDR PC, [PC, #0x14]
220 LDR PC, [PC, #0x14]
221 LDR PC, [PC, #0x14]
222
223 .word INT_Undef_Inst
224 .word INT_Swi
225 .word INT_Abort_Prefetch
226 .word INT_Abort_Data
227 .word INT_Reserved
228 .word INT_IRQ
229 .word INT_FIQ
230
231 ; CALYPSO PLUS TEST MODE - TO BE ERASED
232 .sect ".intvecs"
233
234 _ResetVectorTestMode:
235 B _INT_Bootloader_Start
236 B INT_Undef_Inst
237 B INT_Swi
238 B INT_Abort_Prefetch
239 B INT_Abort_Data
240 B INT_Reserved
241 B INT_IRQ
242 B INT_FIQ
243
244 .else ; CHIPSET = 12
245
246 .sect ".intvecs"
247
248 .if BOARD = 34
249 B _INT_Initialize
250 .elseif BOARD = 35
251 B _INT_Initialize
252 .else
253 .ref _INT_Bootloader_Start
254
255 B _INT_Bootloader_Start
256 .endif
257 B INT_Undef_Inst
258 B INT_Swi
259 B INT_Abort_Prefetch
260 B INT_Abort_Data
261 B INT_Reserved
262 B Vect_IRQ
263 .if WCP_PROF = 1
264 .global _PR_StoreMonteCarloSample
265
266 ; Timing profiler using FIQ - Handle FIQ directly here
267
268 STMFD sp!,{R0-R4, LR} ; Save R0-R4 and LR on FIQ stack
269
270 MOV R0, LR ; Retrieve link register in R0
271 BL _PR_StoreMonteCarloSample ; Store into ring buffer
272 BL _IQ_FIQ_isr ; Ack FIQ
273
274 LDMFD sp!,{R0-R4, LR} ; Restore R0-R4 and LR from FIQ stack
275 SUBS PC, LR, #4 ; return from FIQ
276 .else
277 B Vect_FIQ
278 .endif
279 .endif ; CHIPSET = 12
280
281 ;
282 ; .text
283 ;
284 ; .ref cinit
285
286 .sect ".inttext"
287 .global cinit ; Linker symbol for C variable init.
288
289
290 ; Address definitions in the section where they are used.
291
292 ;
293 ;/* Define the global system stack variable. This is setup by the
294 ; initialization routine. */
295 ;
296 ;extern VOID *TCD_System_Stack;
297 ;
298 .ref _TCD_System_Stack
299 .ref _TCT_System_Limit
300 ;
301 ;
302 ;/* Define the global data structures that need to be initialized by this
303 ; routine. These structures are used to define the system timer management
304 ; HISR. */
305 ;
306 ;extern VOID *TMD_HISR_Stack_Ptr;
307 ;extern UNSIGNED TMD_HISR_Stack_Size;
308 ;extern INT TMD_HISR_Priority;
309 ;
310 .ref _TMD_HISR_Stack_Ptr
311 .ref _TMD_HISR_Stack_Size
312 .ref _TMD_HISR_Priority
313 ;
314 ;
315 ;/* Define extern function references. */
316 ;
317 ;VOID INC_Initialize(VOID *first_available_memory);
318 ;VOID TCT_Interrupt_Context_Save(VOID);
319 ;VOID TCT_Interrupt_Context_Restore(VOID);
320 ;VOID TCC_Dispatch_LISR(INT vector_number);
321 ;VOID TMT_Timer_Interrupt(void);
322 ;
323 .ref _INC_Initialize
324 .ref _TCT_Interrupt_Context_Save
325 .ref _TCT_Interrupt_Context_Restore
326 .ref _TCC_Dispatch_LISR
327 .ref _TMT_Timer_Interrupt
328
329 ;/* Application ISR */
330 .ref _IQ_IRQ_isr
331 .ref _IQ_FIQ_isr
332 ;
333 ; /* Reference pointers defined by the linker */
334 ;
335 .ref .bss
336 .ref end
337
338 ;
339 ;/* Define indirect branching labels for the vector table */
340 ;
341
342 .def INT_Undef_Inst
343 INT_Undef_Inst
344 B arm_undefined ; Undefined
345 ;
346 .def INT_Swi
347 INT_Swi
348 B arm_swi ; Software Generated
349 ;
350 .def INT_Abort_Prefetch
351 INT_Abort_Prefetch
352 B arm_abort_prefetch ; Abort Prefetch
353 ;
354 .def INT_Abort_Data
355 INT_Abort_Data
356 B arm_abort_data ; Abort Data
357 ;
358 .def INT_Reserved
359 INT_Reserved
360 B arm_reserved ; Reserved
361 ;
362 .def Vect_IRQ
363 Vect_IRQ
364 .if TI_NUC_MONITOR = 1
365 B _INT_IRQ
366 .else
367 B INT_IRQ
368 .endif
369 ;
370 .def Vect_FIQ
371 Vect_FIQ
372 .if TI_PROFILER = 1
373 B _INT_FIQ
374 .else
375 B INT_FIQ
376 .endif
377 ;
378
379 ;
380 ;/*************************************************************************/
381 ;/* */
382 ;/* FUNCTION */
383 ;/* */
384 ;/* INT_Initialize */
385 ;/* */
386 ;/* DESCRIPTION */
387 ;/* */
388 ;/* This function sets up the global system stack variable and */
389 ;/* transfers control to the target independent initialization */
390 ;/* function INC_Initialize. Responsibilities of this function */
391 ;/* include the following: */
392 ;/* */
393 ;/* - Setup necessary processor/system control registers */
394 ;/* - Initialize the vector table */
395 ;/* - Setup the system stack pointers */
396 ;/* - Setup the timer interrupt */
397 ;/* - Calculate the timer HISR stack and priority */
398 ;/* - Calculate the first available memory address */
399 ;/* - Transfer control to INC_Initialize to initialize all of */
400 ;/* the system components. */
401 ;/* */
402 ;/* AUTHOR */
403 ;/* */
404 ;/* Barry Sellew, Accelerated Technology, Inc. */
405 ;/* */
406 ;/* CALLED BY */
407 ;/* */
408 ;/* none */
409 ;/* */
410 ;/* CALLS */
411 ;/* */
412 ;/* INC_Initialize Common initialization */
413 ;/* */
414 ;/* INPUTS */
415 ;/* */
416 ;/* None */
417 ;/* */
418 ;/* OUTPUTS */
419 ;/* */
420 ;/* None */
421 ;/* */
422 ;/* HISTORY */
423 ;/* */
424 ;/* NAME DATE REMARKS */
425 ;/* */
426 ;/* B. Sellew 01-19-1996 Created initial version 1.0 */
427 ;/* B. Sellew 01-22-1996 Verified version 1.0 */
428 ;/* */
429 ;/*************************************************************************/
430 ;VOID INT_Initialize(void)
431 ;{
432 .def _c_int00
433 _c_int00
434
435 .include "init.asm"
436
437 addrCS0 .word 0xfffffb00 ; CS0 address space
438
439 .if BOARD = 34
440 CSConfigTable .long CS0_CONFIG
441 CS7_SIZE .equ 0x2000 ; 8 kB
442 CS7_ADDR .equ 0x03800000 ; initial address before toggling nIBOOT
443 SRAM_ADDR .equ 0x03000000 ; Internal SRAM start address
444 SRAM_SIZE .equ 0x00040000 ; 256kB
445 EXTRA_CONF .short 0x013E ; Boot configuration
446 DEF_EXTRA_CONF .short 0x063E ; Default configuration
447 addrCS7 .word 0xFFFFFB08 ; CS7 configuration
448 addrExtraConf .word 0xFFFFFB10 ; Extra configuration
449 armio_in .word 0xFFFE4800 ; ARMIO_IN register address
450 armio_out .word 0xFFFE4802 ; ARMIO_OUT register address
451 .endif
452
453 .if BOARD = 40 | 41
454 EX_MPU_CONF_REG .word 0xFFFEF006 ; Extended MPU configuration register address
455 EX_FLASH_VALUE .short 0x0008 ; set bit to enable A22
456 .endif
457
458 .if CHIPSET = 4
459 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
460 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
461 RHEA_CNTL_REG .word 0xFFFFF900 ; RHEA control register address
462
463
464 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
465 ; Use DPLL, Divide by 1
466 DPLL_CONTROL_RST .short 0x2002 ; Configure DPLL in default state
467 RHEA_CONTROL_RST .short 0xFF22 ; Set access factor in order to access the DPLL register
468 ; independently of the ARM clock
469 .elseif CHIPSET = 6
470 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
471 CNTLCLK_26MHZ_SELECTOR .short 0x0040 ; VTCXO_26 selector
472
473 .elseif CHIPSET = 7
474 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
475 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
476 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
477 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
478
479 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
480 ; Use DPLL, Divide by 1
481 DPLL_CONTROL_RST .short 0x2002 ; Configure DPLL in default state
482 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
483 ENABLE_DU_MASK .short 0xF7FF ; Mask to Enable the DU module
484 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
485
486 .elseif CHIPSET = 8
487 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
488 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
489 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
490 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
491
492 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
493 ; Use DPLL, Divide by 1
494 DPLL_CONTROL_RST .short 0x2002 ; Configure DPLL in default state
495 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
496 ENABLE_DU_MASK .short 0xF7FF ; Mask to Enable the DU module
497 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
498
499 .elseif CHIPSET = 10
500 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
501 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
502 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
503 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
504
505 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
506 ; Use DPLL, Divide by 1
507 DPLL_CONTROL_RST .short 0x2002 ; Configure DPLL in default state
508 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
509 ENABLE_DU_MASK .short 0xF7FF ; Mask to Enable the DU module
510 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
511
512 .elseif CHIPSET = 11
513 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
514 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
515 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
516 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
517
518 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
519 ; Use DPLL, Divide by 1
520 DPLL_CONTROL_RST .short 0x2002 ; Configure DPLL in default state
521 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
522 ENABLE_DU_MASK .short 0xF7FF ; Mask to Enable the DU module
523 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
524
525 .elseif CHIPSET = 12
526 DBG_DMA_P2 .word 0xFFFEF02C ; DBG_DMA_P2 register address
527 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
528 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
529 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
530 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
531
532 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
533 ; Use DPLL, Divide by 1
534 DPLL_CONTROL_RST .short 0x2006 ; Configure DPLL in default state
535 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
536 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
537 DBG_DMA_P2_RST .short 0x0002 ; DBG_DMA_P2 register reset value
538 .endif ; CHIPSET = 4 or 6 or 7 or 8 or 10 or 11 or 12
539
540
541 c_cinit .long cinit
542
543 .def _INT_Initialize
544 _INT_Initialize
545
546 ;
547 ; Configuration of ARM clock and DPLL frequency
548 ;
549 .if CHIPSET = 4
550 ;
551 ; Configure RHEA access factor in order to allow the access of DPLL register
552 ;
553 ldr r1,RHEA_CNTL_REG ; Load address of RHEA control register in R1
554 ldrh r2,RHEA_CONTROL_RST ; Load RHEA configuration value in R2
555 strh r2,[r1] ; Store DPLL reset value in RHEA control register
556
557 ;
558 ; Configure DPLL register with reset value
559 ;
560 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
561 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
562 strh r2,[r1] ; Store DPLL reset value in DPLL register
563
564 ;
565 ; Wait that DPLL goes in BYPASS mode
566 ;
567 Wait_DPLL_Bypass
568 ldr r2,[r1] ; Load DPLL register
569 and r2,r2,#1 ; Perform a mask on bit 0
570 cmp r2,#1 ; Compare DPLL lock bit
571 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
572
573 ;
574 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
575 ; generate ARM clock with division factor of 1.
576 ;
577 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
578 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
579 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
580
581 .elseif CHIPSET = 6
582
583 ;
584 ; Set VTCXO_26MHZ bit to '1' in case of the VTCXO clock is 26MHz instead
585 ; of 13MHz.
586 ;
587 ldr r1, CNTL_ARM_CLK_REG ; Load CLKM base register address in R1
588 ldrh r2, [r1,#2] ; Load contents of CNTL_CLK register in R2
589 ldr r0, CNTLCLK_26MHZ_SELECTOR ; Load configuration of 26MHz selector
590 orr r0, r0, r2;
591 strh r0, [r1,#2];
592
593 ; Wait a while until clock is stable (required for AvengerII)
594 mov r0,#0x100
595 WaitAWhile1:
596 sub r0, r0, #1
597 cmp r0, #0
598 bne WaitAWhile1
599
600 .elseif CHIPSET = 7
601 ;
602 ; Configure DPLL register with reset value
603 ;
604 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
605 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
606 strh r2,[r1] ; Store DPLL reset value in DPLL register
607
608 ;
609 ; Wait that DPLL goes in BYPASS mode
610 ;
611 Wait_DPLL_Bypass
612 ldr r2,[r1] ; Load DPLL register
613 and r2,r2,#1 ; Perform a mask on bit 0
614 cmp r2,#1 ; Compare DPLL lock bit
615 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
616
617 ;
618 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
619 ; generate ARM clock with division factor of 1.
620 ;
621 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
622 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
623 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
624
625 ;
626 ; Disable/Enable the DU module by setting/resetting bit 11 to '1'/'0'
627 ;
628 ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF
629 ;ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
630 ldrh r2,ENABLE_DU_MASK ; Load mask to write in Extra Control register CONF
631 ldrh r0,[r1] ; Load Extra Control register CONF in r0
632 ;orr r0,r0,r2 ; Disable DU module
633 and r0,r0,r2 ; Enable DU module
634 strh r0,[r1] ; Store configuration in Extra Control register CONF
635
636 ;
637 ; Disable all MPU protections
638 ;
639 ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register
640 ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register
641 strh r2,[r1] ; Store reset value of MPU_CTL register
642
643 .elseif CHIPSET = 8
644 ;
645 ; Configure DPLL register with reset value
646 ;
647 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
648 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
649 strh r2,[r1] ; Store DPLL reset value in DPLL register
650
651 ;
652 ; Wait that DPLL goes in BYPASS mode
653 ;
654 Wait_DPLL_Bypass
655 ldr r2,[r1] ; Load DPLL register
656 and r2,r2,#1 ; Perform a mask on bit 0
657 cmp r2,#1 ; Compare DPLL lock bit
658 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
659
660 ;
661 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
662 ; generate ARM clock with division factor of 1.
663 ;
664 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
665 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
666 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
667
668 ;
669 ; Disable/Enable the DU module by setting/resetting bit 11 to '1'/'0'
670 ;
671 ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF
672 ;ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
673 ldrh r2,ENABLE_DU_MASK ; Load mask to write in Extra Control register CONF
674 ldrh r0,[r1] ; Load Extra Control register CONF in r0
675 ;orr r0,r0,r2 ; Disable DU module
676 and r0,r0,r2 ; Enable DU module
677 strh r0,[r1] ; Store configuration in Extra Control register CONF
678
679 ;
680 ; Disable all MPU protections
681 ;
682 ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register
683 ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register
684 strh r2,[r1] ; Store reset value of MPU_CTL register
685
686 .elseif CHIPSET = 10
687 ;
688 ; Configure DPLL register with reset value
689 ;
690 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
691 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
692 strh r2,[r1] ; Store DPLL reset value in DPLL register
693
694 ;
695 ; Wait that DPLL goes in BYPASS mode
696 ;
697 Wait_DPLL_Bypass
698 ldr r2,[r1] ; Load DPLL register
699 and r2,r2,#1 ; Perform a mask on bit 0
700 cmp r2,#1 ; Compare DPLL lock bit
701 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
702
703 ;
704 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
705 ; generate ARM clock with division factor of 1.
706 ;
707 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
708 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
709 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
710
711 ;
712 ; Disable/Enable the DU module by setting/resetting bit 11 to '1'/'0'
713 ;
714 ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF
715 ;ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
716 ldrh r2,ENABLE_DU_MASK ; Load mask to write in Extra Control register CONF
717 ldrh r0,[r1] ; Load Extra Control register CONF in r0
718 ;orr r0,r0,r2 ; Disable DU module
719 and r0,r0,r2 ; Enable DU module
720 strh r0,[r1] ; Store configuration in Extra Control register CONF
721
722 ;
723 ; Disable all MPU protections
724 ;
725 ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register
726 ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register
727 strh r2,[r1] ; Store reset value of MPU_CTL register
728
729 .elseif CHIPSET = 11
730 ;
731 ; Configure DPLL register with reset value
732 ;
733 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
734 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
735 strh r2,[r1] ; Store DPLL reset value in DPLL register
736
737 ;
738 ; Wait that DPLL goes in BYPASS mode
739 ;
740 Wait_DPLL_Bypass
741 ldr r2,[r1] ; Load DPLL register
742 and r2,r2,#1 ; Perform a mask on bit 0
743 cmp r2,#1 ; Compare DPLL lock bit
744 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
745
746 ;
747 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
748 ; generate ARM clock with division factor of 1.
749 ;
750 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
751 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
752 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
753
754 ;
755 ; Disable/Enable the DU module by setting/resetting bit 11 to '1'/'0'
756 ;
757 ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF
758 ;ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
759 ldrh r2,ENABLE_DU_MASK ; Load mask to write in Extra Control register CONF
760 ldrh r0,[r1] ; Load Extra Control register CONF in r0
761 ;orr r0,r0,r2 ; Disable DU module
762 and r0,r0,r2 ; Enable DU module
763 strh r0,[r1] ; Store configuration in Extra Control register CONF
764
765 ;
766 ; Disable all MPU protections
767 ;
768 ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register
769 ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register
770 strh r2,[r1] ; Store reset value of MPU_CTL register
771
772 .elseif CHIPSET = 12
773
774 .if BOARD = 6
775 ; Configure DBG_DMA_P2 reg => GPO_2 output pin for EVA4
776 ldr r1,DBG_DMA_P2 ; Load address of DBG_DMA_P2 register in R1
777 ldrh r2,DBG_DMA_P2_RST ; Load DBG_DMA_P2 reset value in R2
778 strh r2,[r1] ; Store reset value in register
779 ;
780 .endif ; BOARD = 6
781
782 ;
783 ; Configure DPLL register with reset value
784 ;
785 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
786 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
787 strh r2,[r1] ; Store DPLL reset value in DPLL register
788
789 ;
790 ; Wait that DPLL goes in BYPASS mode
791 ;
792 Wait_DPLL_Bypass
793 ldr r2,[r1] ; Load DPLL register
794 and r2,r2,#1 ; Perform a mask on bit 0
795 cmp r2,#1 ; Compare DPLL lock bit
796 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
797
798 ;
799 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
800 ; generate ARM clock with division factor of 1.
801 ;
802 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
803 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
804 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
805
806 ;
807 ; Disable the DU module by setting bit 11 to '1'
808 ;
809 ; ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF
810 ; ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
811 ; ldrh r0,[r1] ; Load Extra Control register CONF in r0
812 ; orr r0,r0,r2 ; Disable DU module
813 ; strh r0,[r1] ; Store configuration in Extra Control register CONF
814
815 ;
816 ; Disable all MPU protections
817 ;
818 ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register
819 ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register
820 strh r2,[r1] ; Store reset value of MPU_CTL register
821
822 .endif ; CHIPSET = 4 or 6 or 7 or 8 or 10 or 11 or 12
823
824 ;
825 ; Wait-state configuration of external and internal memories
826 ;
827 .if BOARD = 34
828 ;
829 ; Wait states for Perseus - see IQ_InitWaitStates for details
830 ;
831
832
833 mov r0, #NUM_CS_REGS ; number of chip selects to configure
834 ldr r1, addrCS0 ; first CS register
835 ldr r2, CSConfigTable ; table of values to program
836
837 ConfigCS:
838 ldrh r3,[r2]
839 strh r3,[r1]
840 add r1, r1, #2
841 add r2, r2, #2
842 sub r0, r0, #1
843 cmp r0, #0
844 bne ConfigCS
845
846 bl Ensure_external_access
847 bl Copy_code_into_CS7
848 bl Toggle_nIBoot
849
850 ; Wait a while - not quite sure why, but it is required for Avenger II
851 mov r0,#0x100
852 WaitAWhile2:
853 sub r0, r0, #1
854 cmp r0, #0
855 bne WaitAWhile2
856
857 bl Clear_Internal_SRAM ; This is required if the BSS is not in SRAM
858
859 .elseif BOARD = 35
860
861 ldr r1,addrCS0
862 ldrh r2,CS0_MEM_REG ; CS0 initialization
863 strh r2,[r1]
864 ldrh r2,CS1_MEM_REG ; CS1 initialization
865 strh r2,[r1,#0x2]
866 ldrh r2,CS2_MEM_REG ; CS2 initialization
867 strh r2,[r1,#0x4]
868 ldrh r2,CS7_MEM_REG ; CS7 initialization
869 strh r2,[r1,#0x8]
870 ldrh r2,CS6_MEM_REG ; CS6 initialization
871 strh r2,[r1,#0xC]
872 mov r2,#API_ADAPT ; API-RHEA configuration
873 strh r2,[r1,#0xE]
874
875 bl Ensure_external_access
876 bl Copy_code_into_CS7
877 bl Toggle_nIBoot
878 bl Clear_Internal_SRAM ; This is required if the BSS is not in SRAM
879
880 .else
881
882 ldr r1,addrCS0
883 .if CHIPSET != 12
884 ldrh r2,CS0_MEM_REG ; ROM initialization
885 strh r2,[r1] ; CS0
886
887 ldrh r2,CS1_MEM_REG ; RAM Initialization
888 strh r2,[r1,#2] ; CS1
889
890 ldrh r2,CS2_MEM_REG ; RAM Initialization
891 strh r2,[r1,#4] ; CS2
892
893 ldrh r2,CS3_MEM_REG ; Parallel I/O on B-Sample
894 strh r2,[r1,#6] ; CS3 (unused on EVA4?)
895
896 ldrh r2,CS4_MEM_REG ; Latch on B-Sample
897 strh r2,[r1,#0xa] ; CS4 (unused on EVA4)
898
899 .else
900
901 ldrh r2,CS0_MEM_REG ; CALYPSO PLUS TEST MODE - TO BE ERASED - FLASH Initialization
902 strh r2,[r1,#0x0] ; CS0
903
904 ldrh r2,CS5_MEM_REG ; FLASH Initialization
905 strh r2,[r1,#0xA] ; CS5
906
907 ldrh r2,CS4_MEM_REG ; RAM Initialization
908 strh r2,[r1,#0x8] ; CS4
909
910 .endif
911
912 .if CHIPSET = 3
913 ldrh r2,CS6_MEM_REG ; Internal SRAM initialization
914 strh r2,[r1,#0xc] ; CS6 Internal RAM
915
916 .elseif CHIPSET = 4
917 ldrh r2,CS6_MEM_REG ; Internal SRAM initialization
918 strh r2,[r1,#0xc] ; CS6 Internal RAM
919
920 ldrh r2,CS7_MEM_REG ; Internal SRAM initialization
921 strh r2,[r1,#0x8] ; CS7 Internal Boot RAM
922
923 .elseif CHIPSET = 5
924 ldrh r2,CS6_MEM_REG ; Internal SRAM initialization
925 strh r2,[r1,#0xc] ; CS6 Internal RAM
926
927 .elseif CHIPSET = 6
928 ldrh r2,CS6_MEM_REG ; Internal SRAM initialization
929 strh r2,[r1,#0xc] ; CS6 Internal RAM
930
931 .elseif CHIPSET = 7
932 ldrh r2,CS6_MEM_REG ; Internal SRAM initialization
933 strh r2,[r1,#0xc] ; CS6 Internal RAM
934
935 ldrh r2,CS7_MEM_REG ; Internal SRAM initialization
936 strh r2,[r1,#0x8] ; CS7 Internal Boot ROM
937
938 .elseif CHIPSET = 8
939 ldrh r2,CS6_MEM_REG ; Internal SRAM initialization
940 strh r2,[r1,#0xc] ; CS6 Internal RAM
941
942 ldrh r2,CS7_MEM_REG ; Internal SRAM initialization
943 strh r2,[r1,#0x8] ; CS7 Internal Boot ROM
944
945 .elseif CHIPSET = 10
946 ldrh r2,CS6_MEM_REG ; Internal SRAM initialization
947 strh r2,[r1,#0xc] ; CS6 Internal RAM
948
949 ldrh r2,CS7_MEM_REG ; Internal SRAM initialization
950 strh r2,[r1,#0x8] ; CS7 Internal Boot ROM
951
952 .elseif CHIPSET = 11
953 ldrh r2,CS6_MEM_REG ; Internal SRAM initialization
954 strh r2,[r1,#0xc] ; CS6 Internal RAM
955
956 ldrh r2,CS7_MEM_REG ; Internal SRAM initialization
957 strh r2,[r1,#0x8] ; CS7 Internal Boot ROM
958 .endif ; CHIPSET = 3 or 4 or 5 or 6 or 7 or 8 or 10 or 11
959
960 ldrh r2,CTL_MEM_REG ; API-RHEA configuration
961 strh r2,[r1,#0xe]
962
963 .endif ; BOARD = 34 | 35
964
965 .if BOARD = 40 | 41
966 ; /* On D-Sample Board, use A22 mode (ADD(22) instead of CS4) to be able to
967 ; address 8 Mbytes especially with CS0 (Flash) & CS3 (External Peripherals) */
968 ldr r1,EX_MPU_CONF_REG
969 ldrh r2,[r1]
970 ldr r0,EX_FLASH_VALUE
971 orr r0, r0, r2
972 strh r0,[r1]
973 .endif
974
975 ;
976 ; /* Insure that the processor is in supervisor mode. */
977 ;
978 MRS a1,CPSR ; Pickup current CPSR
979 BIC a1,a1,#MODE_MASK ; Clear the mode bits
980 ORR a1,a1,#SUP_MODE ; Set the supervisor mode bits
981 ORR a1,a1,#LOCKOUT ; Insure IRQ and FIQ interrupts are
982 ; locked out
983 MSR CPSR,a1 ; Setup the new CPSR
984 ;
985
986 ;
987 ;
988 ; REWORK OF .bss INITIALIZATION - start
989 ; Creation of INT_memset and INT_memcpy, respectively identical to memset and
990 ; memcpy from the rts library of compiler V2.51/2.54.
991 ; They are used to make the initialization of the .bss section and the load
992 ; of the internal ram code not dependent to the 32-bit alignment.
993 ; The old code used for the initialization and the load used a loop with
994 ; 4-byte increment, assuming the 32-bit alignment of the .bss section.
995 ; This alignment is not necessary true.
996 ;
997 ; /* Clear the un-initialized global and static C data areas. */
998 ; Initialize the system stack pointer a first time to allow use of memset function
999 ; which needs stack.
1000 ; The system stack pointers will be fully initialized after having cleared
1001 ; the BSS area. */
1002 ;
1003 LDR a1,StackSegment ; Pickup the begining address from .cmd file
1004 ; (is aligned on 8 byte boundary)
1005
1006 MOV a2,#SYSTEM_SIZE ; Pickup system stack size
1007 SUB a2,a2,#4 ; Subtract one word for first addr
1008 ADD a3,a1,a2 ; Build start of system stack area
1009
1010 MOV sp,a3 ; Setup initial stack pointer
1011
1012 STMFD sp!,{a1-a4} ; Save a1-a4 registers to stack
1013
1014 LDR a1,BSS_Start ; Pickup the start of the BSS area
1015 LDR a3,BSS_End ; Pickup the end of the BSS area
1016 SUB a3,a3,a1 ; Calculate size of the BSS area
1017 MOV a2,#0 ; Clear value in a2
1018
1019 BL _INT_memset ; Clear the BSS area using memset function
1020
1021 .if LONG_JUMP >= 3 ;
1022 LDR a1,BSS_IntMem_Start ; Pickup the start of the BSS area
1023 LDR a3,BSS_IntMem_End ; Pickup the end of the BSS area
1024 SUB a3,a3,a1 ; Calculate size of the BSS area
1025 MOV a2,#0 ; Clear value in a2
1026
1027 BL _INT_memset ; Clear the BSS area using memset function
1028
1029 .endif
1030
1031 LDMFD sp!,{a1-a4} ; Restore a1-a4 registers from stack
1032
1033 ; REWORK OF .bss INITIALIZATION - end
1034
1035 ;
1036 ; /* Setup the vectors loaded flag to indicate to other routines in the
1037 ; system whether or not all of the default vectors have been loaded.
1038 ; If INT_Loaded_Flag is 1, all of the default vectors have been loaded.
1039 ; Otherwise, if INT_Loaded_Flag is 0, registering an LISR cause the
1040 ; default vector to be loaded. In the THUMB this variable is always
1041 ; set to 1. All vectors must be setup by this function. */
1042 ; INT_Loaded_Flag = 0;
1043 ;
1044 MOV a1,#1 ; All vectors are assumed loaded
1045 LDR a2,Loaded_Flag ; Build address of loaded flag
1046 STR a1,[a2,#0] ; Initialize loaded flag
1047 ;
1048 ; /* Initialize the system stack pointers. This is done after the BSS is
1049 ; cleared because the TCD_System_Stack pointer is a BSS variable! It is
1050 ; assumed that the .cmd file is written to direct where these stacks should
1051 ; be allocated and to align them on double word boundaries.
1052 ;
1053 LDR a1,StackSegment ; Pickup the begining address from .cmd file
1054 ; (is aligned on 8 byte boundary)
1055 MOV a2,#SYSTEM_SIZE ; Pickup system stack size
1056 SUB a2,a2,#4 ; Subtract one word for first addr
1057 ADD a3,a1,a2 ; Build start of system stack area
1058 MOV v7,a1 ; Setup initial stack limit
1059 LDR a4,System_Limit ; Pickup system stack limit address
1060 STR v7,[a4, #0] ; Save stack limit
1061 MOV sp,a3 ; Setup initial stack pointer
1062 LDR a4,System_Stack ; Pickup system stack address
1063 STR sp,[a4, #0] ; Save stack pointer
1064 MOV a2,#IRQ_STACK_SIZE ; Pickup IRQ stack size in bytes
1065 ADD a3,a3,a2 ; Allocate IRQ stack area
1066 MRS a1,CPSR ; Pickup current CPSR
1067 BIC a1,a1,#MODE_MASK ; Clear the mode bits
1068 ORR a1,a1,#IRQ_MODE ; Set the IRQ mode bits
1069 MSR CPSR,a1 ; Move to IRQ mode
1070 MOV sp,a3 ; Setup IRQ stack pointer
1071 MOV a2,#FIQ_STACK_SIZE ; Pickup FIQ stack size in bytes
1072 ADD a3,a3,a2 ; Allocate FIQ stack area
1073 MRS a1,CPSR ; Pickup current CPSR
1074 BIC a1,a1,#MODE_MASK ; Clear the mode bits
1075 ORR a1,a1,#FIQ_MODE ; Set the FIQ mode bits
1076 MSR CPSR,a1 ; Move to the FIQ mode
1077 MOV sp,a3 ; Setup FIQ stack pointer
1078
1079 MRS a1,CPSR ; Pickup current CPSR
1080 BIC a1,a1,#MODE_MASK ; Clear the mode bits
1081 ORR a1,a1,#ABORT_MODE ; Set the Abort mode bits
1082 MSR CPSR,a1 ; Move to the Abort mode
1083 LDR sp,Exception_Stack ; Setup Abort stack pointer
1084
1085 MRS a1,CPSR ; Pickup current CPSR
1086 BIC a1,a1,#MODE_MASK ; Clear the mode bits
1087 ORR a1,a1,#UNDEF_MODE ; Set the Undefined mode bits
1088 MSR CPSR,a1 ; Move to the Undefined mode
1089 LDR sp,Exception_Stack ; Setup Undefined stack pointer
1090 ; (should never be used)
1091
1092 ; go to Supervisor Mode
1093 MRS a1,CPSR ; Pickup current CPSR
1094 BIC a1,a1,#MODE_MASK ; Clear mode bits
1095 ORR a1,a1,#SUP_MODE ; Set the supervisor mode bits
1096 MSR CPSR,a1 ; All interrupt stacks are setup,
1097 ; return to supervisor mode
1098 ;
1099 ; /* Define the global data structures that need to be initialized by this
1100 ; routine. These structures are used to define the system timer
1101 ; management HISR. */
1102 ; TMD_HISR_Stack_Ptr = (VOID *) a3;
1103 ; TMD_HISR_Stack_Size = TIMER_SIZE;
1104 ; TMD_HISR_Priority = TIMER_PRIORITY;
1105 ;
1106 ; TMD_HISR_Stack_Ptr points at the top (the lowest address) of the allocated
1107 ; area. The Timer HISR (called "SYSTEM H") and its related stack will be created
1108 ; in TMI_Initialize(). The current stack pointer will be set at the bottom (the
1109 ; lowest address) of the expected area.
1110
1111 LDR a4,HISR_Stack_Ptr ; Pickup variable's address
1112 ADD a3,a3,#4 ; Increment to next available word
1113 STR a3,[a4, #0] ; Setup timer HISR stack pointer
1114 MOV a2,#TIMER_SIZE ; Pickup the timer HISR stack size
1115 BIC a2,a2,#3 ; Insure word alignment
1116 ADD a3,a3,a2 ; Allocate the timer HISR stack
1117 ; from available memory
1118 LDR a4,HISR_Stack_Size ; Pickup variable's address
1119 STR a2,[a4, #0] ; Setup timer HISR stack size
1120 MOV a2,#TIMER_PRIORITY ; Pickup timer HISR priority (0-2)
1121 LDR a4,HISR_Priority ; Pickup variable's address
1122 STR a2,[a4, #0] ; Setup timer HISR priority
1123
1124 .if CHIPSET = 12
1125 ; This sequence must be always done in order to download the interrupt
1126 ; vector remapping
1127 MOV V1, a3 ; Save a3 register
1128 BL _f_load_int_mem ; Download FLASH to Internal RAM
1129 MOV a3, V1 ; Restore a3 register
1130 .else
1131
1132 .if LONG_JUMP >= 3
1133 MOV V1, a3 ; Save a3 register
1134 BL _f_load_int_mem ; Download FLASH to Internal RAM
1135 MOV a3, V1 ; Restore a3 register
1136 .endif
1137
1138 .endif ; CHIPSET != 12
1139
1140 ; We now fill up the System, IRQ, FIQ and System Timer HISR stacks with 0xFE for
1141 ; checking the status of the stacks later.
1142 ; inputs:
1143 ; a3 still has the bottom of all four stacks and is aligned.
1144 ; algorithm:
1145 ; We start from the top of all four stacks (*System_Limit), which is
1146 ; necessarily aligned. We store 0xFEFEFEFE until we have filled the
1147 ; bottom of the fourth stack
1148 ; outputs:
1149 ; memory has 0xFE on all four stacks: System, FIQ, IRQ and System Timer HISR
1150 ; a3 still has the bottom of all four stacks
1151
1152 LDR a2,System_Limit ; pickup system stack limit address
1153 LDR a1,[a2] ; a1 = StackSegment
1154 MOV a4,#0FEh ; use this and the next 7 instructons to set a4 = 0xFEFEFEFE
1155 STRB a4,[a1, #0]
1156 STRB a4,[a1, #1]
1157 STRB a4,[a1, #2]
1158 STRB a4,[a1, #3]
1159 LDR a4,[a1],#4 ; stored first word, move to second
1160
1161 fill_stack:
1162 STR a4,[a1],#4 ; store a word and increment by four
1163 CMP a1,a3 ; is this the last address?
1164 BLT fill_stack ; if not, loop back
1165
1166 ;
1167 ; Perform auto-initialization. if cinit is -1, then there is none.
1168 ;
1169 LDR r0, c_cinit
1170 CMN r0, #1
1171 BLNE _auto_init
1172 ;
1173 ; /* Call INC_Initialize with a pointer to the first available memory
1174 ; address after the compiler's global data. This memory may be used
1175 ; by the application. */
1176 ; INC_Initialize(first_available_memory);
1177 ;
1178 MOV a1,a3 ; Pass the first available memory
1179 B _INC_Initialize ; to high-level initialization
1180 ;}
1181 ;
1182
1183
1184 .if BOARD=35 | BOARD=34
1185
1186 ;/*
1187 ; * FUNCTION
1188 ; *
1189 ; * Ensure_external_access
1190 ; */
1191 Ensure_external_access:
1192 ;AI_ResetBit(4); // request shared mem clock
1193 ldr r1, armio_out
1194 ldrh r2, [r1]
1195 bic r2, r2, #0x10
1196 strh r2, [r1]
1197
1198 ;while(AI_ReadBit(5)!=1); // wait for acknowledge
1199 ack:
1200 ldr r1, armio_in
1201 ldrh r2, [r1]
1202 and r2, r2, #0x20
1203 cmp r2, #0x20
1204 bne ack
1205 bx lr ; Return to caller
1206
1207 ;/*
1208 ; * FUNCTION
1209 ; *
1210 ; * Copy_code_into_CS7
1211 ; */
1212 Copy_code_into_CS7:
1213 ldr r1, addrExtraConf
1214 ldr r3, DEF_EXTRA_CONF
1215 strh r3, [r1] ; ensure CS7 selects internal memory
1216
1217 mov r0, #CS7_SIZE ; size of CS7 memory in bytes
1218 mov r1, #CS7_ADDR ; destination
1219 mov r2, #0 ; source
1220 CopyIntCode:
1221 ldr r3,[r2]
1222 str r3,[r1]
1223 add r1, r1, #4
1224 add r2, r2, #4
1225 sub r0, r0, #4
1226 cmp r0, #0
1227 bne CopyIntCode
1228
1229 ldr r1, addrCS7
1230 ldr r2, [r1]
1231 bic r2, r2, #0x80 ; Write Enable OFF on CS7
1232 strh r2, [r1]
1233 bx lr ; Return to caller
1234
1235 ;/*
1236 ; * FUNCTION
1237 ; *
1238 ; * Toggle_nIBoot
1239 ; */
1240 Toggle_nIBoot:
1241 ldr r1, addrExtraConf ; Address of Extra Conf Register
1242 ldr r3, EXTRA_CONF ; set CS7 at address zero
1243 strh r3, [r1]
1244 bx lr ; Return to caller
1245
1246 ;/*
1247 ; * FUNCTION
1248 ; *
1249 ; * Clear_Internal_SRAM
1250 ; */
1251 Clear_Internal_SRAM:
1252 mov r0, #SRAM_ADDR ; r0 points to SRAM start
1253 mov r1, #SRAM_SIZE
1254 add r1, r0, r1 ; r1 points to SRAM end
1255 mov r2, #0
1256
1257 ClearSram:
1258 str r2,[r0], #4
1259 cmp r0, r1 ; done?
1260 bne ClearSram ; no - loop
1261 bx lr ; Return to caller
1262
1263 .endif ; BOARD=34 | BOARD=35
1264
1265 ;
1266 ;/*************************************************************************/
1267 ;/* */
1268 ;/* FUNCTION */
1269 ;/* */
1270 ;/* INT_Vectors_Loaded */
1271 ;/* */
1272 ;/* DESCRIPTION */
1273 ;/* */
1274 ;/* This function returns the flag that indicates whether or not */
1275 ;/* all the default vectors have been loaded. If it is false, */
1276 ;/* each LISR register also loads the ISR shell into the actual */
1277 ;/* vector table. */
1278 ;/* */
1279 ;/* AUTHOR */
1280 ;/* */
1281 ;/* Barry Sellew, Accelerated Technology, Inc. */
1282 ;/* */
1283 ;/* CALLED BY */
1284 ;/* */
1285 ;/* TCC_Register_LISR Register LISR for vector */
1286 ;/* */
1287 ;/* CALLS */
1288 ;/* */
1289 ;/* None */
1290 ;/* */
1291 ;/* INPUTS */
1292 ;/* */
1293 ;/* None */
1294 ;/* */
1295 ;/* OUTPUTS */
1296 ;/* */
1297 ;/* None */
1298 ;/* */
1299 ;/* HISTORY */
1300 ;/* */
1301 ;/* NAME DATE REMARKS */
1302 ;/* */
1303 ;/* B. Sellew 01-19-1996 Created initial version 1.0 */
1304 ;/* B. Sellew 01-22-1996 Verified version 1.0 */
1305 ;/* */
1306 ;/*************************************************************************/
1307 ;INT INT_Vectors_Loaded(void)
1308 ;{
1309 .def $INT_Vectors_Loaded
1310 $INT_Vectors_Loaded ; Dual-state interworking veneer
1311 .state16
1312 BX pc
1313 NOP
1314 .state32
1315 B _INT_Vectors_Loaded
1316 ;
1317 .def _INT_Vectors_Loaded
1318 _INT_Vectors_Loaded
1319 ;
1320 ; /* Just return the loaded vectors flag. */
1321 ; return(INT_Loaded_Flag);
1322 ;
1323 MOV a1,#1 ; Always return TRUE since there
1324 ; are really only two normal
1325 ; vectors IRQ & FIQ
1326 BX lr ; Return to caller
1327 ;}
1328 ;
1329 ;
1330 ;/*************************************************************************/
1331 ;/* */
1332 ;/* FUNCTION */
1333 ;/* */
1334 ;/* INT_Setup_Vector */
1335 ;/* */
1336 ;/* DESCRIPTION */
1337 ;/* */
1338 ;/* This function sets up the specified vector with the new vector */
1339 ;/* value. The previous vector value is returned to the caller. */
1340 ;/* */
1341 ;/* AUTHOR */
1342 ;/* */
1343 ;/* Barry Sellew, Accelerated Technology, Inc. */
1344 ;/* */
1345 ;/* CALLED BY */
1346 ;/* */
1347 ;/* Application */
1348 ;/* TCC_Register_LISR Register LISR for vector */
1349 ;/* */
1350 ;/* CALLS */
1351 ;/* */
1352 ;/* None */
1353 ;/* */
1354 ;/* INPUTS */
1355 ;/* */
1356 ;/* vector Vector number to setup */
1357 ;/* new Pointer to new assembly */
1358 ;/* language ISR */
1359 ;/* */
1360 ;/* OUTPUTS */
1361 ;/* */
1362 ;/* old vector contents */
1363 ;/* */
1364 ;/* HISTORY */
1365 ;/* */
1366 ;/* NAME DATE REMARKS */
1367 ;/* */
1368 ;/* B. Sellew 01-19-1996 Created initial version 1.0 */
1369 ;/* B. Sellew 01-22-1996 Verified version 1.0 */
1370 ;/* */
1371 ;/*************************************************************************/
1372 ;VOID *INT_Setup_Vector(INT vector, VOID *new)
1373 ;{
1374 .def $INT_Setup_Vector
1375 $INT_Setup_Vector ; Dual-state interworking veneer
1376 .state16
1377 BX pc
1378 NOP
1379 .state32
1380 B _INT_Setup_Vector
1381 ;
1382 .def _INT_Setup_Vector
1383 _INT_Setup_Vector
1384 ;
1385 ;VOID *old_vector; /* Old interrupt vector */
1386 ;VOID **vector_table; /* Pointer to vector table */
1387 ;
1388 ; /* Calculate the starting address of the actual vector table. */
1389 ; vector_table = (VOID **) 0;
1390 ;
1391 ; /* Pickup the old interrupt vector. */
1392 ; old_vector = vector_table[vector];
1393 ;
1394 ; /* Setup the new interrupt vector. */
1395 ; vector_table[vector] = new;
1396 ;
1397 ; /* Return the old interrupt vector. */
1398 ; return(old_vector);
1399 ;
1400 MOV a1,#0 ; This routine is not applicable to
1401 ; THUMB, return a NULL pointer
1402 BX lr ; Return to caller
1403 ;}
1404 ;
1405 ;
1406 ;
1407 ;
1408 ;/*************************************************************************/
1409 ;/* */
1410 ;/* FUNCTIONS */
1411 ;/* */
1412 ;/* INT_EnableIRQ, INT_DisableIRQ */
1413 ;/* */
1414 ;/* DESCRIPTION */
1415 ;/* */
1416 ;/* This function enable/disable IRQ/FIQ in current mode */
1417 ;/* */
1418 ;/*************************************************************************/
1419 ;
1420 .global $INT_EnableIRQ
1421 $INT_EnableIRQ:
1422 .state16
1423 BX pc
1424 nop
1425
1426 .state32
1427 MRS a1, CPSR ; read current PSR
1428 BIC a1,a1,#MODE_MASK ; remove all mode bits
1429 ORR a1,a1,#IRQ_MODE ; retrieve desired mode
1430 MSR CPSR,a1 ; IRQ mode
1431
1432 MRS a1, CPSR ; read current PSR
1433 BIC a1,a1,#LOCKOUT ; interrupt lockout value
1434 MSR CPSR,a1 ; Lockout interrupts
1435
1436 BIC a1,a1,#MODE_MASK ; remove all mode bits
1437 ORR a1,a1,#SUP_MODE
1438 MSR CPSR,a1 ; Lockout interrupts
1439
1440 add a1, pc, #1 ; back to Thumb mode
1441 bx a1
1442
1443 .state16
1444 BX lr ; Return to caller
1445
1446 ;
1447 ;
1448 .global $INT_DisableIRQ
1449 $INT_DisableIRQ:
1450 .state16
1451 BX pc
1452 nop
1453
1454 .state32
1455 MRS a1, CPSR ; read current PSR
1456 BIC a1,a1,#MODE_MASK ; remove all mode bits
1457 ORR a1,a1,#IRQ_MODE ; retrieve desired mode
1458 MSR CPSR,a1 ; IRQ mode
1459
1460 MRS a1, CPSR ; read current PSR
1461 ORR a1,a1,#LOCKOUT ; Build interrupt lockout value
1462 MSR CPSR,a1 ; Lockout interrupts
1463
1464 BIC a1,a1,#MODE_MASK ; remove all mode bits
1465 ORR a1,a1,#SUP_MODE
1466 MSR CPSR,a1 ; Lockout interrupts
1467
1468 add a1, pc, #1 ; back to Thumb mode
1469 bx a1
1470
1471 .state16
1472 BX lr ; Return to caller
1473 ;
1474 ;
1475 ;/*************************************************************************/
1476 ;/* */
1477 ;/* FUNCTION */
1478 ;/* */
1479 ;/* INT_Retrieve_Shell */
1480 ;/* */
1481 ;/* DESCRIPTION */
1482 ;/* */
1483 ;/* This function retrieves the pointer to the shell interrupt */
1484 ;/* service routine. The shell interrupt service routine calls */
1485 ;/* the LISR dispatch routine. */
1486 ;/* */
1487 ;/* AUTHOR */
1488 ;/* */
1489 ;/* Barry Sellew, Accelerated Technology, Inc. */
1490 ;/* */
1491 ;/* CALLED BY */
1492 ;/* */
1493 ;/* TCC_Register_LISR Register LISR for vector */
1494 ;/* */
1495 ;/* CALLS */
1496 ;/* */
1497 ;/* None */
1498 ;/* */
1499 ;/* INPUTS */
1500 ;/* */
1501 ;/* vector Vector number to setup */
1502 ;/* */
1503 ;/* OUTPUTS */
1504 ;/* */
1505 ;/* shell pointer */
1506 ;/* */
1507 ;/* HISTORY */
1508 ;/* */
1509 ;/* NAME DATE REMARKS */
1510 ;/* */
1511 ;/* B. Sellew 01-19-1996 Created initial version 1.0 */
1512 ;/* B. Sellew 01-22-1996 Verified version 1.0 */
1513 ;/* */
1514 ;/*************************************************************************/
1515 ;VOID *INT_Retrieve_Shell(INT vector)
1516 ;{
1517 .def $INT_Retrieve_Shell
1518 $INT_Retrieve_Shell ; Dual-state interworking veneer
1519 .state16
1520 BX pc
1521 NOP
1522 .state32
1523 B _INT_Retrieve_Shell
1524 ;
1525 .def _INT_Retrieve_Shell
1526 _INT_Retrieve_Shell
1527 ;
1528 ; /* Return the LISR Shell interrupt routine. */
1529 ; return(INT_Vectors[vector]);
1530 ;
1531 MOV a1,#0 ; This routine is not applicable to
1532 ; THUMB, return a NULL pointer
1533 BX lr ; Return to caller
1534 ;}
1535 ;
1536 ;
1537 ;
1538 ;/* The following section contains default interrupt handlers. */
1539 ;
1540 .if TI_NUC_MONITOR = 1
1541 ; define a new section to be mapped independently
1542 .sect ".irqtext"
1543
1544 .def _INT_IRQ
1545 .global _INT_IRQ
1546 _INT_IRQ
1547 .else
1548 .def INT_IRQ
1549 INT_IRQ
1550 .endif
1551
1552 ;
1553 ; /* Call Prepare for IRQ interrupt processing by calling
1554 ; TCT_Interrupt_Context_Save. */
1555 STMDB sp!,{a1-a4} ; Save a1-a4 on temporary IRQ stack
1556
1557 ;BUG correction 1st part -------------------
1558 ;It looks like there is an issue with ARM7 IRQ masking in the CPSR register
1559 ;which leads to crashes in Nucleus+ scheduler.
1560 ;Basically the code below (correct as LOCKOUT = 0xC0) is used in many places by N+ but do not
1561 ;prevent from having an interrupt after the execution of the third line (I mean execution, not
1562 ;fetch).
1563 ; MRS a1,CPSR ; Pickup current CPSR
1564 ; ORR a1,a1,#LOCKOUT ; Build interrupt lockout value
1565 ; MSR CPSR,a1 ; Lockout interrupts
1566 ; * IRQ INTERRUPT ! *
1567 ; Next instructions...
1568 ;
1569 ;SW workaround:
1570 ;When a task is interrupted at this point an interrupted context is stored on its task and will
1571 ;be resumed later on at the next instruction but to make a long story short it leads to some
1572 ;problem as the OS does not expect to be interrupted there.
1573 ;Further testing tends to show that the CPSR *seems* to be loaded with the proper masking value
1574 ;but that the IRQ is still triggered (has been hardwarewise requested during the instruction
1575 ;exectution by the ARM7 core?)
1576 MRS a1,spsr ; check for the IRQ bug:
1577 TST a1,#080h ; if the I - flag is set,
1578 BNE IRQBUG ; then postpone execution of this IRQ
1579 ;Bug correction 1st part end ---------------
1580
1581 SUB a4,lr,#4 ; Save IRQ's lr (return address)
1582 BL _TCT_Interrupt_Context_Save ; Call context save routine
1583
1584 .if TI_NUC_MONITOR = 1
1585 ; Log the IRQ call entry
1586 .global _ti_nuc_monitor_LISR_log
1587 BL _ti_nuc_monitor_LISR_log ; Call the LISR Log function.
1588 .endif
1589
1590 ;
1591 ; /* On actuall hardware, a register must be examined to see what the
1592 ; IRQ interrupt was caused from. For default processing, the
1593 ; timer is the only IRQ interrupt source. It is assumed that further
1594 ; timer interrupts are disabled upon this call. */
1595 ;
1596 BL _IQ_IRQ_isr ; Call int. service routine
1597
1598 .if TI_NUC_MONITOR = 1
1599 ; Log the IRQ exit
1600 .global _ti_nuc_monitor_LISR_log_end
1601 BL _ti_nuc_monitor_LISR_log_end ; Call the LISR end function.
1602 .endif
1603
1604 ;
1605 ; /* IRQ interrupt processing is complete. Restore context- Never
1606 ; returns! */
1607 B _TCT_Interrupt_Context_Restore
1608
1609 ;BUG correction 2nd part ------------------
1610 IRQBUG: LDMFD sp!,{a1-a4} ; return from interrupt
1611 SUBS pc,r14,#4
1612 ;BUG correction 2nd part end --------------
1613
1614 ;
1615 .if TI_NUC_MONITOR = 1
1616 .sect ".inttext"
1617 .endif
1618 ;
1619 .if TI_PROFILER = 1
1620 ; define a new section to be mapped independently
1621 .sect ".fiqtext"
1622
1623 .def _INT_FIQ
1624 .global _INT_FIQ
1625 _INT_FIQ
1626 .else
1627 .def INT_FIQ
1628 INT_FIQ
1629 .endif
1630
1631 .if TI_PROFILER = 1
1632 ; Warning :
1633 ; This code has been added for profiliing purpose.
1634 ; It removes all other FIQ.
1635 .global _ti_profiler_handler
1636 ; Timing profiler using FIQ - Handle FIQ directly here
1637 STMFD sp!,{R0-R4, LR} ; Save R0-R4 and LR on FIQ stack
1638
1639 MOV R0, LR ; Retrieve link register in R0
1640 BL _ti_profiler_handler ; Store into buffer
1641 BL _IQ_FIQ_isr ; Call the FIQ ISR
1642 LDMFD sp!,{R0-R4, LR} ; Restore R0-R4 and LR from FIQ stack
1643 SUBS PC, LR, #4 ; return from FIQ
1644 .else
1645
1646 ;
1647 ; /* Call Prepare for FIQ interrupt processing by calling
1648 ; TCT_Interrupt_Context_Save. */
1649 STMDB sp!,{a1-a4} ; Save a1-a4 on temporary FIQ stack
1650 SUB a4,lr,#4 ; Save FIQ's lr (return address)
1651 BL _TCT_Interrupt_Context_Save ; Call context save routine
1652 ;
1653 ; /* On actuall hardware, a register must be examined to see what the
1654 ; FIQ interrupt was caused from. For default processing, the
1655 ; test is the only FIQ interrupt source. */
1656 ;
1657 ; /* Replace this with a call to your own ISR */
1658 BL _IQ_FIQ_isr ; Call the FIQ ISR
1659
1660 ;
1661 ; /* FIQ interrupt processing is complete. Restore context- Never
1662 ; returns! */
1663 B _TCT_Interrupt_Context_Restore
1664
1665 .endif
1666
1667 .if TI_PROFILER = 1
1668 .sect ".inttext"
1669 .endif
1670
1671 ;***************************************************************
1672 ;* CONSTANT TABLE *
1673 ;***************************************************************
1674
1675 ;
1676 ; /* Define all the global addresses used in this section */
1677 ;
1678
1679 ; internal/external RAM
1680 .if CHIPSET = 3 | CHIPSET = 5 | CHIPSET = 6
1681 RAM_SIZE .equ 0x40000 ; size (in bytes) of internal RAM
1682 RAM_LOW .equ 0x3000000 ; first address of internal RAM
1683 .elseif CHIPSET = 4
1684 RAM_SIZE .equ 0x40000 ; size (in bytes) of internal RAM
1685 RAM_LOW .equ 0x800000 ; first address of internal RAM
1686 .elseif CHIPSET = 7 | CHIPSET = 8 | CHIPSET = 10 | CHIPSET = 11 | CHIPSET = 12
1687 .if L1_GPRS = 1
1688 RAM_SIZE .equ 0x200000 ; size (in bytes) of external RAM
1689 RAM_LOW .equ 0x1000000 ; first address of external RAM
1690 .else ; GSM ONLY
1691 RAM_SIZE .equ 0x80000 ; size (in bytes) of internal RAM
1692 RAM_LOW .equ 0x800000 ; first address of internal RAM
1693 .endif
1694 .endif
1695
1696 RAM_HIGH .equ RAM_LOW + RAM_SIZE ; first address after internal/external RAM
1697
1698
1699 .global exception_stack ; top address of SVC mode stack
1700
1701 .global _xdump_buffer ; first address of state data
1702
1703 .global stack_segment ; address of the top of the system stack
1704
1705 ;
1706 ; /* Define exception functions */
1707 ;
1708 .ref _dar_exception
1709
1710 XDUMP_STACK_SIZE .equ 20
1711
1712 ; layout of xdump buffer:
1713 ; struct xdump_s {
1714 ; long registers[16] // svc mode registers
1715 ; long cpsr // svc mode CPSR
1716 ; long exception // magic word + index of vector taken
1717 ; long stack[20] // bottom 20 words of usr mode stack
1718 ; }
1719
1720 arm_undefined:
1721 stmfd r13!,{r11,r12} ; store r12 for Xdump_buffer pointer, r11 for index
1722 mov r11,#1
1723 b save_regs
1724
1725 arm_swi:
1726 stmfd r13!,{r11,r12} ; store r12 for Xdump_buffer pointer, r11 for index
1727 mov r11,#2
1728 b save_regs
1729
1730 arm_abort_prefetch:
1731 stmfd r13!,{r11,r12} ; store r12 for Xdump_buffer pointer, r11 for index
1732 mov r11,#3
1733 b save_regs
1734
1735
1736 arm_abort_data:
1737 stmfd r13!,{r11,r12} ; store r12 for Xdump_buffer pointer, r11 for index
1738 mov r11,#4
1739 b save_regs
1740
1741 arm_reserved:
1742 ldr r13,Exception_Stack ; should never happen, but mode is unknown at this point
1743 stmfd r13!,{r11,r12} ; store r12 for Xdump_buffer pointer, r11 for index
1744 mov r11,#5
1745 b save_regs
1746
1747 save_regs:
1748 ldr r12,Xdump_buffer
1749 str r14,[r12,#4*15] ; save r14_abt (original PC) into r15 slot
1750
1751 stmia r12,{r0-r10} ; save unbanked registers (except r11 and r12)
1752 ldmfd r13!,{r0,r1} ; get original r11 and r12
1753 str r0,[r12,#4*11] ; save original r11
1754 str r1,[r12,#4*12] ; save original r12
1755 mrs r0,spsr ; get original psr
1756 str r0,[r12,#4*16] ; save original cpsr
1757
1758 mrs r1,cpsr ; save mode psr
1759 bic r2,r1,#0x1f ; psr with mode bits cleared
1760 and r0,r0,#0x1f ; get original mode bits
1761 add r0,r0,r2
1762
1763 msr cpsr,r0 ; move to pre-exception mode
1764 str r13,[r12,#4*13] ; save original SP
1765 str r14,[r12,#4*14] ; save original LR
1766 msr cpsr,r1 ; restore mode psr
1767
1768 ; r11 has original index
1769 orr r10,r11,#0xDE<<24; r10 = 0xDEAD0000 + index of vector taken
1770 orr r10,r10,#0xAD<<16
1771 str r10,[r12,#4*17] ; save magic + index
1772
1773 mov r0,r11 ; put index into 1st argument
1774 b _dar_exception
1775
1776 .global $exception ; export function
1777
1778 $exception: ; Veneer function
1779 .ref _exception
1780 .state16
1781 adr r0,_exception
1782 bx r0
1783 .align
1784 .state32
1785 .def _exception
1786 _exception:
1787 ldr r12,Xdump_buffer ; redundant unless _exception is called
1788 ldr r11,[r12,#4*13] ; get svc mode r13
1789 add r12,r12,#4*18 ; base of stack buffer
1790
1791 ; check if svc r13(sp) is within internal/external RAM. It *could* be invalid.
1792 ; we boldly assume stack is only within internal RAM except for GPRS build on
1793 ; Calypso chipset : stack is within external RAM
1794 .if CHIPSET = 7 | CHIPSET = 8 | CHIPSET = 10 | CHIPSET = 11
1795 .if L1_GPRS = 1
1796 ; if GPRS, check for internal RAM as well as 2Mbytes of external RAM
1797 cmp r11,#0x800000 ; INTERNAL RAM_LOW
1798 blt nostack
1799 mov r0, #0x880000 ; INTERNAL RAM_HIGH
1800 sub r0,r0,#XDUMP_STACK_SIZE
1801 cmp r11,r0
1802 blt stack_range
1803 ; was not less than 0x880000, so check for external RAM
1804 cmp r11,#RAM_LOW
1805 blt nostack
1806 mov r0,#RAM_HIGH
1807 sub r0,r0,#XDUMP_STACK_SIZE
1808 cmp r11,r0
1809 bge nostack
1810 .else ; GSM ONLY
1811 cmp r11,#RAM_LOW
1812 blt nostack
1813 mov r0,#RAM_HIGH
1814 sub r0,r0,#XDUMP_STACK_SIZE
1815 cmp r11,r0
1816 bge nostack
1817 .endif
1818 .endif
1819
1820 stack_range:
1821 ldmfd r11!,{r0-r9} ; copy ten stack words..
1822 stmia r12!,{r0-r9}
1823 ldmfd r11!,{r0-r9} ; copy ten stack words..
1824 stmia r12!,{r0-r9}
1825
1826 nostack:
1827 STACKS .equ SYSTEM_SIZE + IRQ_STACK_SIZE + FIQ_STACK_SIZE + TIMER_SIZE
1828 .ref _dar_reset
1829 ; we're finished saving all state. Now execute C code for more flexibility.
1830 ; set up a stack for this C call
1831 LDR a1,StackSegment ; Pickup the begining address from .cmd file
1832 ; (is aligned on 8 byte boundary)
1833 MOV a2,#STACKS ; Pickup all stacks size
1834 ADD a2,a2,#0x80 ; Add 128 to get past all used data
1835 ADD a3,a1,a2
1836 MOV sp,a3 ; Setup exception stack pointer
1837 b _dar_reset
1838
1839
1840 BSS_Start
1841 .word .bss
1842 ;
1843 BSS_End
1844 .word end
1845 ;
1846 .if LONG_JUMP >= 3
1847 .align 4
1848 BSS_IntMem_Start: .field _S_D_Mem,32
1849 .align 4
1850 BSS_IntMem_End: .field _E_D_Mem,32
1851 .endif
1852
1853 StackSegment
1854 .word stack_segment
1855 ;
1856 Loaded_Flag
1857 .word _INT_Loaded_Flag
1858 ;
1859 System_Limit
1860 .word _TCT_System_Limit
1861 ;
1862 System_Stack
1863 .word _TCD_System_Stack
1864 ;
1865 HISR_Stack_Ptr
1866 .word _TMD_HISR_Stack_Ptr
1867 ;
1868 HISR_Stack_Size
1869 .word _TMD_HISR_Stack_Size
1870 ;
1871 HISR_Priority
1872 .word _TMD_HISR_Priority
1873 ;
1874 Exception_Stack
1875 .word exception_stack
1876 ;
1877 Xdump_buffer
1878 .word _xdump_buffer
1879 ;
1880 ; The following code is pulled from rts.src, which is part of the
1881 ; TI tools installation.
1882 ;
1883 ;***************************************************************************
1884 ;* PROCESS INITIALIZATION TABLE.
1885 ;*
1886 ;* THE TABLE CONSISTS OF A SEQUENCE OF RECORDS OF THE FOLLOWING FORMAT:
1887 ;*
1888 ;* .word <length of data (bytes)>
1889 ;* .word <address of variable to initialize>
1890 ;* .word <data>
1891 ;*
1892 ;* THE INITIALIZATION TABLE IS TERMINATED WITH A ZERO LENGTH RECORD.
1893 ;*
1894 ;***************************************************************************
1895 ;****auto_init(register int *table)
1896 ;****{
1897 ;**** register int length;
1898 ;**** register int *addr;
1899 ;****
1900 ;**** while (length = *table++)
1901 ;**** {
1902 ;**** addr = (int *)*table++;
1903 ;**** while (length)
1904 ;**** {
1905 ;**** if (length > 3)
1906 ;**** {
1907 ;**** *addr++ = *table++;
1908 ;**** length -= 4;
1909 ;**** }
1910 ;**** else
1911 ;**** {
1912 ;**** *(char *)addr++ = *(char *)table++;
1913 ;**** length--;
1914 ;**** }
1915 ;**** }
1916 ;**** }
1917 ;****}
1918
1919 tbl_addr: .set R0
1920 var_addr: .set R1
1921 length: .set R3
1922 data: .set R4
1923
1924 _auto_init:
1925 B rec_chk
1926
1927 record:
1928 ;*------------------------------------------------------
1929 ;* PROCESS AN INITIALIZATION RECORD
1930 ;*------------------------------------------------------
1931 LDR var_addr, [tbl_addr], #4
1932
1933 copy:
1934 ;*------------------------------------------------------
1935 ;* COPY THE INITIALIZATION DATA
1936 ;*------------------------------------------------------
1937 CMP length, #3
1938
1939 LDRHI data, [tbl_addr], #4
1940 STRHI data, [var_addr], #4 ; COPY A WORD OF DATA
1941 SUBHI length, length, #4 ; OR ...
1942 LDRLSB data, [tbl_addr], #1 ;
1943 STRLSB data, [var_addr], #1 ; COPY A BYTE OF DATA
1944 SUBLS length, length, #1
1945
1946 CMP length, #0 ; CONTINUE TO COPY IF
1947 BNE copy ; LENGTH IS NONZERO
1948
1949 ANDS length, tbl_addr, #0x3 ; MAKE SURE THE ADDRESS
1950 RSBNE length, length, #0x4 ; IS WORD ALIGNED
1951 ADDNE tbl_addr, tbl_addr, length ;
1952
1953 rec_chk:LDR length, [tbl_addr], #4 ; PROCESS NEXT
1954 CMP length, #0 ; RECORD IF LENGTH IS
1955 BNE record ; NONZERO
1956
1957 MOV PC, LR
1958 ;
1959
1960 ;
1961 ; Creation of INT_memset and INT_memcpy, respectively identical to memset and
1962 ; memcpy from the rts library of compiler 2.51/2.54.
1963 ; They are used to make the initialization of the .bss section and the load
1964 ; of the internal ram code not dependent to the 32-bit alignment.
1965 ; The old code used for the initialization and the load used a loop with
1966 ; 4-byte increment, assuming the 32-bit alignment of the .bss section.
1967 ; This alignment is not necessary true.
1968 ;
1969 ;******************************************************************************
1970 ;* INT_memset - INITIALIZE MEMORY WITH VALUE *
1971 ;******************************************************************************
1972 ;* MEMSET32.ASM - 32 BIT STATE - v2.51 *
1973 ;* Copyright (c) 1996-2003 Texas Instruments Incorporated *
1974 ;******************************************************************************
1975
1976 ;****************************************************************************
1977 ;* INT_memset - INITIALIZE MEMORY WITH VALUE.
1978 ;*
1979 ;* Same memset defined in rts.src.
1980 ;* Used in INT_Initialize to clear bss area.
1981 ;* Used in f_load_int_mem() function to clear internal memory space used
1982 ;* for data and code.
1983 ;* The memset function defined in rts library is loaded into internal memory,
1984 ;* then, it can not be used in either INT_Initialize, or f_load_int_mem().
1985 ;*
1986 ;* C Prototype : void *INT_memset(void *s, int c, size_t n);
1987 ;* C++ Prototype : void *std::INT_memset(void *s, int c, std::size_t n);
1988 ;*
1989 ;****************************************************************************
1990 ;*
1991 ;* o DESTINATION LOCATION IS IN r0
1992 ;* o INITIALIZATION VALUE IS IN r1
1993 ;* o NUMBER OF BYTES TO INITIALIZE IS IN r2
1994 ;*
1995 ;* o ORIGINAL DESTINATION LOCATION RETURNED IN r0
1996 ;****************************************************************************
1997 .state32
1998 .def _INT_memset
1999
2000 _INT_memset:
2001 STMFD SP!, {R0, LR} ; save R0 also since original dst
2002 ; address is returned.
2003
2004 TST R0, #3 ; check for word alignment
2005 BEQ _word_aligned
2006
2007 CMP R2, #0 ; set bytes until there are no more
2008 ; to set or until address is aligned
2009 _unaligned_loop:
2010 STRHIB R1, [R0], #1
2011 SUBHIS R2, R2, #1
2012 TSTHI R0, #3
2013 BNE _unaligned_loop
2014
2015 CMP R2, #0 ; return early if no more bytes
2016 LDMEQFD SP!, {R0, PC} ; to set.
2017
2018 _word_aligned:
2019 AND R1, R1, #255 ; be safe since prototype has value as
2020 ; as an int rather than unsigned char
2021
2022 ORR R1, R1, R1, LSL #8 ; replicate byte in 2nd byte of
2023 ; register
2024
2025 CMP R2,#4 ; are at least 4 bytes being set
2026 BCC _INT_memset3
2027
2028 ORR R1, R1, R1, LSL #16 ; replicate byte in upper 2 bytes
2029 ; of register. note that each of
2030 ; the bottom 2 bytes already contain
2031 ; the byte value from above.
2032
2033 CMP R2,#8 ; are at least 8 bytes being set
2034 BCC _INT_memset7
2035
2036 MOV LR,R1 ; copy bits into another register so
2037 ; 8 bytes at a time can be copied.
2038 ; use LR since it is already being
2039 ; saved/restored.
2040
2041 CMP R2,#16 ; are at least 16 bytes being set
2042 BCC _INT_memset15
2043
2044 STMFD SP!, {R4} ; save regs needed by 16 byte copies
2045
2046 MOV R4, R1 ; copy bits into 2 other registers so
2047 MOV R12, R1 ; 16 bytes at a time can be copied
2048
2049 SUB R3, R2, #15 ; set up loop count
2050 AND R2, R2, #15 ; determine number of bytes to set
2051 ; after setting 16 byte blocks
2052
2053 _INT_memset16_loop: ; set blocks of 16 bytes
2054 STMIA R0!, {R1, R4, R12, LR}
2055 SUBS R3, R3, #16
2056 BHI _INT_memset16_loop
2057
2058 LDMFD SP!, {R4} ; resotre regs used by 16 byte copies
2059
2060 _INT_memset15: ; may still be as many as 15 bytes to
2061 ; set. the address in R0 is guaranteed
2062 ; to be word aligned here.
2063
2064 TST R2, #8 ; are at least 8 bytes being set
2065 STMNEIA R0!, {R1, LR}
2066
2067
2068 _INT_memset7: ; may still be as many as 7 bytes to
2069 ; set. the address in R0 is guaranteed
2070 ; to be word aligned here.
2071
2072 TST R2, #4 ; are at least 4 bytes being set
2073 STRNE R1, [R0], #4
2074
2075 _INT_memset3: ; may still be as many as 3 bytes to
2076 ; set. the address in R0 is guaranteed
2077 ; to be word aligned here.
2078
2079 TST R2, #2 ; are there at least 2 more bytes to
2080 STRNEH R1, [R0], #2 ; set. the address in R0 is guaranteed
2081 ; to be half-word aligned here.
2082
2083 TST R2, #1 ; is there one remaining byte to set
2084 STRNEB R1, [R0]
2085
2086
2087 LDMFD SP!, {R0, PC} ; restore regs and return
2088
2089
2090 ;******************************************************************************
2091 ;* INT_memcpy - COPY CHARACTERS FROM SOURCE TO DEST *
2092 ;******************************************************************************
2093 ;* MEMCPY32.ASM - 32 BIT STATE - v2.51 *
2094 ;* Copyright (c) 1996-2003 Texas Instruments Incorporated *
2095 ;******************************************************************************
2096
2097 ;****************************************************************************
2098 ;* INT_memcpy - COPY CHARACTERS FROM SOURCE TO DEST
2099 ;*
2100 ;* Same as C_MEMCPY defined in rts.src.
2101 ;* Used in INT_Initialize to download code into internal memory space.
2102 ;* The memcpy function defined in rts library is loaded into internal memory.
2103 ;* then, it can not be used in f_load_int_mem().
2104 ;*
2105 ;****************************************************************************
2106 ;*
2107 ;* o DESTINATION LOCATION IS IN r0
2108 ;* o SOURCE LOCATION IS IN r1
2109 ;* o NUMBER OF CHARACTERS TO BE COPIED IS IN r2
2110 ;****************************************************************************
2111 .state32
2112 .def _INT_memcpy
2113
2114 _INT_memcpy:
2115 CMP r2, #0 ; CHECK FOR n == 0
2116 BXEQ lr ;
2117
2118 STMFD sp!, {r0, lr} ; SAVE RETURN VALUE AND ADDRESS
2119
2120 TST r1, #0x3 ; CHECK ADDRESS ALIGNMENT
2121 BNE _unaln ; IF NOT WORD ALIGNED, HANDLE SPECIALLY
2122 TST r0, #0x3 ;
2123 BNE _saln ;
2124
2125 _aln: CMP r2, #16 ; CHECK FOR n >= 16
2126 BCC _l16 ;
2127
2128 STMFD sp!, {r4} ;
2129 SUB r2, r2, #16 ;
2130 _c16: LDMIA r1!, {r3, r4, r12, lr} ; COPY 16 BYTES
2131 STMIA r0!, {r3, r4, r12, lr} ;
2132 SUBS r2, r2, #16 ;
2133 BCS _c16 ;
2134 LDMFD sp!, {r4} ;
2135 ADDS r2, r2, #16 ; RETURN IF DONE
2136 LDMEQFD sp!, {r0, pc} ;
2137
2138 _l16: ANDS r3, r2, #0xC ;
2139 BEQ _cp1 ;
2140 BICS r2, r2, #0xC ;
2141 ADR r12, _4line - 16 ;
2142 ADD pc, r12, r3, LSL #2 ;
2143
2144 _4line: LDR r3, [r1], #4 ; COPY 4 BYTES
2145 STR r3, [r0], #4 ;
2146 LDMEQFD sp!, {r0, pc} ; CHECK FOR n == 0
2147 B _cp1 ;
2148
2149 LDMIA r1!, {r3, r12} ; COPY 8 BYTES
2150 STMIA r0!, {r3, r12} ;
2151 LDMEQFD sp!, {r0, pc} ; CHECK FOR n == 0
2152 B _cp1 ;
2153
2154 LDMIA r1!, {r3, r12, lr} ; COPY 12 BYTES
2155 STMIA r0!, {r3, r12, lr} ;
2156 LDMEQFD sp!, {r0, pc} ; CHECK FOR n == 0
2157
2158 _cp1: SUBS r2, r2, #1 ;
2159 ADRNE r3, _1line - 4 ; SETUP TO COPY 1 - 3 BYTES...
2160 ADDNE pc, r3, r2, LSL #4 ;
2161
2162 _1line: LDRB r3, [r1], #1 ; COPY 1 BYTE
2163 STRB r3, [r0], #1 ;
2164 LDMFD sp!, {r0, pc} ;
2165
2166 LDRH r3, [r1], #2 ; COPY 2 BYTES
2167 STRH r3, [r0], #2 ;
2168 LDMFD sp!, {r0, pc} ;
2169 NOP ;
2170
2171 LDRH r3, [r1], #2 ; COPY 3 BYTES
2172 STRH r3, [r0], #2 ;
2173 LDRB r3, [r1], #1 ;
2174 STRB r3, [r0], #1 ;
2175 LDMFD sp!, {r0, pc} ;
2176
2177 _unaln: LDRB r3, [r1], #1 ; THE ADDRESSES ARE NOT WORD ALIGNED.
2178 STRB r3, [r0], #1 ; COPY BYTES UNTIL THE SOURCE IS
2179 SUBS r2, r2, #1 ; WORD ALIGNED OR THE COPY SIZE
2180 LDMEQFD sp!, {r0, pc} ; BECOMES ZERO
2181 TST r1, #0x3 ;
2182 BNE _unaln ;
2183
2184 _saln: TST r0, #0x1 ; IF THE ADDRESSES ARE OFF BY 1 BYTE
2185 BNE _off1 ; JUST BYTE COPY
2186
2187 TST r0, #0x2 ; IF THE ADDRESSES ARE NOW WORD ALIGNED
2188 BEQ _aln ; GO COPY. ELSE THEY ARE OFF BY 2, SO
2189 ; GO SHORT WORD COPY
2190
2191 _off2: SUBS r2, r2, #4 ; COPY 2 BYTES AT A TIME...
2192 BCC _c1h ;
2193 _c2: LDR r3, [r1], #4 ; START BY COPYING CHUNKS OF 4,
2194 .if .TMS470_BIG
2195 STRH r3, [r0, #2] ;
2196 MOV r3, r3, LSR #16 ;
2197 STRH r3, [r0], #4 ;
2198 .else
2199 STRH r3, [r0], #4 ;
2200 MOV r3, r3, LSR #16 ;
2201 STRH r3, [r0, #-2] ;
2202 .endif
2203 SUBS r2, r2, #4 ;
2204 BCS _c2 ;
2205 CMN r2, #4 ;
2206 LDMEQFD sp!, {r0, pc} ;
2207
2208 _c1h: ADDS r2, r2, #2 ; THEN COPY THE ODD BYTES.
2209 LDRCSH r3, [r1], #2 ;
2210 STRCSH r3, [r0], #2 ;
2211 SUBCS r2, r2, #2 ;
2212 ADDS r2, r2, #1 ;
2213 LDRCSB r3, [r1], #1 ;
2214 STRCSB r3, [r0], #1 ;
2215 LDMFD sp!, {r0, pc} ;
2216
2217 _off1: SUBS r2, r2, #4 ; COPY 1 BYTE AT A TIME...
2218 BCC _c1b ;
2219 _c1: LDR r3, [r1], #4 ; START BY COPYING CHUNKS OF 4,
2220 .if .TMS470_BIG
2221 STRB r3, [r0, #3] ;
2222 MOV r3, r3, LSR #8 ;
2223 STRB r3, [r0, #2] ;
2224 MOV r3, r3, LSR #8 ;
2225 STRB r3, [r0, #1] ;
2226 MOV r3, r3, LSR #8 ;
2227 STRB r3, [r0], #4 ;
2228 .else
2229 STRB r3, [r0], #4 ;
2230 MOV r3, r3, LSR #8 ;
2231 STRB r3, [r0, #-3] ;
2232 MOV r3, r3, LSR #8 ;
2233 STRB r3, [r0, #-2] ;
2234 MOV r3, r3, LSR #8 ;
2235 STRB r3, [r0, #-1] ;
2236 .endif
2237 SUBS r2, r2, #4 ;
2238 BCS _c1 ;
2239
2240 _c1b: ADDS r2, r2, #4 ; THEN COPY THE ODD BYTES.
2241 LDMEQFD sp!, {r0, pc} ;
2242 _lp1: LDRB r3, [r1], #1 ;
2243 STRB r3, [r0], #1 ;
2244 SUBS r2, r2, #1 ;
2245 BNE _lp1 ;
2246 LDMFD sp!, {r0, pc} ;
2247
2248 .end
2249