FreeCalypso > hg > tcs211-pirelli

comparison chipsetsw/drivers/drv_core/sys_map.h @ 0:509db1a7b7b8

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
initial import: leo2moko-r1
author Space Falcon <falcon@ivan.Harhan.ORG>
date Mon, 01 Jun 2015 03:24:05 +0000
parents
children
comparison
equal deleted inserted replaced
-1:000000000000 0:509db1a7b7b8
1 /* @(#) nom : sys_map.h SID: 1.2 date : 05/23/03 */
2 /* Filename: sys_map.h */
3 /* Version: 1.2 */
4 /******************************************************************************
5 * WIRELESS COMMUNICATION SYSTEM DEVELOPMENT
6 *
7 * (C) 2002 Texas Instruments France. All rights reserved
8 *
9 * Author : Francois AMAND
10 *
11 *
12 * Important Note
13 * --------------
14 *
15 * This S/W is a preliminary version. It contains information on a product
16 * under development and is issued for evaluation purposes only. Features
17 * characteristics, data and other information are subject to change.
18 *
19 * The S/W is furnished under Non Disclosure Agreement and may be used or
20 * copied only in accordance with the terms of the agreement. It is an offence
21 * to copy the software in any way except as specifically set out in the
22 * agreement. No part of this document may be reproduced or transmitted in any
23 * form or by any means, electronic or mechanical, including photocopying and
24 * recording, for any purpose without the express written permission of Texas
25 * Instruments Inc.
26 *
27 ******************************************************************************
28 *
29 * FILE NAME: sys_map.h
30 *
31 *
32 * PURPOSE: Memory mapping of the CALYPSO PLUS chip.
33 *
34 *
35 * FILE REFERENCES:
36 *
37 * Name IO Description
38 * ------------- -- ---------------------------------------------
39 *
40 *
41 *
42 * EXTERNAL VARIABLES:
43 *
44 * Source:
45 *
46 * Name Type IO Description
47 * ------------- --------------- -- ------------------------------
48 *
49 *
50 *
51 * EXTERNAL REFERENCES:
52 *
53 * Name Description
54 * ------------------ -------------------------------------------------------
55 *
56 *
57 *
58 * ABNORMAL TERMINATION CONDITIONS, ERROR AND WARNING MESSAGES:
59 *
60 *
61 *
62 * ASSUMPTION, CONSTRAINTS, RESTRICTIONS:
63 *
64 *
65 *
66 * NOTES:
67 *
68 *
69 *
70 * REQUIREMENTS/FUNCTIONAL SPECIFICATION REFERENCES:
71 *
72 *
73 *
74 *
75 * DEVELOPMENT HISTORY:
76 *
77 * Date Name(s) Version Description
78 * ----------- -------------- ------- -------------------------------------
79 * 11-Oct-2002 Francois AMAND 0.0.1 First implementation
80 *
81 * ALGORITHM:
82 *
83 *
84 *****************************************************************************/
85
86 #include "chipset.cfg"
87
88 #if (CHIPSET == 12)
89
90 #ifndef __SYS_MAP_H__
91 #define __SYS_MAP_H__
92
93 /****************************************************************************
94 * STROBE 0 MAPPING
95 ***************************************************************************/
96
97 #define C_MAP_TPU_BASE 0xFFFF1000L // CS2 : TPU registers
98 #define C_MAP_I2C_BASE 0xFFFF2800L // CS5 : I2C registers
99 #define C_MAP_UWIRE_BASE 0xFFFF4000L // CS8 : UWIRE registers
100 #define C_MAP_UART_IRDA_BASE 0xFFFF5000L // CS10 : UART IRDA registers
101 #define C_MAP_UART_MODEM1_BASE 0xFFFF5800L // CS11 : UART MODEM 1 registers
102 #define C_MAP_UART_UIR_BASE 0xFFFF6000L // CS12 : UART UIR register
103 #define C_MAP_RIF_BASE 0xFFFF7000L // CS14 : RIF registers
104 #define C_MAP_TPU_RAM_BASE 0xFFFF9000L // CS18 : TPU RAM
105 #define C_MAP_DPLL_BASE 0xFFFF9800L // CS19 : DPLL register
106 #define C_MAP_LCD_IF_BASE 0xFFFFA000L // CS20 : LCD registers
107 #define C_MAP_USIM_BASE 0xFFFFA800L // CS21 : USIM registers
108 #define C_MAP_USB_BASE 0xFFFFB000L // CS22 : USB registers
109 #define C_MAP_GEA_BASE 0xFFFFC000L // CS24 : GEA registers
110 #define C_MAP_MMC_SD_BASE 0xFFFFC800L // CS25 : MMC/SD registers
111 #define C_MAP_MS_BASE 0xFFFFD000L // CS26 : Memory Stick registers
112 #define C_MAP_CPORT_BASE 0xFFFFD800L // CS27 : C-Port registers
113 #define C_MAP_UART_MODEM2_BASE 0xFFFFE000L // CS28 : UART MODEM 2 registers
114 #define C_MAP_DMA_BASE 0xFFFFE800L // CS29 : DMA registers
115 #define C_MAP_WD_TIMER_BASE 0xFFFFF800L // CS31 : Watchdog TIMER registers
116 #define C_MAP_WD_TIMER_SEC_BASE 0xFFFFF880L // CS31 : Secure Watchdog TIMER registers
117 #define C_MAP_RHEA_BASE 0xFFFFF900L // CS31 : RHEA bridge registers
118 #define C_MAP_INTH_BASE 0xFFFFFA00L // CS31 : INTH registers
119 #define C_MAP_INTH_SEC_BASE 0xFFFFFA80L // CS31 : Secure INTH registers
120 #define C_MAP_MEMIF_BASE 0xFFFFFB00L // CS31 : MEMIF registers
121 #define C_MAP_PRRM_BASE 0xFFFFFC00L // CS31 : PRRM (Protected Ressource Reset Management) registers
122 #define C_MAP_CLKM_BASE 0xFFFFFD00L // CS31 : CLOCKM registers
123 #define C_MAP_JTAG_ID_CODE_BASE 0xFFFFFE00L // CS31 : JTAG ID code registers
124 #define C_MAP_EMPU_BASE 0xFFFFFF00L // CS31 : EMPU registers
125
126
127
128 /****************************************************************************
129 * STROBE 1 MAPPING
130 ***************************************************************************/
131
132 #define C_MAP_SIM_BASE 0xFFFE0000L // CS0 : SIM registers
133 #define C_MAP_TSP_BASE 0xFFFE0800L // CS1 : TSP registers
134 #define C_MAP_RTC_BASE 0xFFFE1800L // CS3 : RTC registers
135 #define C_MAP_ULPD_BASE 0xFFFE2000L // CS4 : ULPD registers
136 #define C_MAP_SPI_BASE 0xFFFE3000L // CS6 : SPI registers
137 #define C_MAP_TIMER1_BASE 0xFFFE3800L // CS7 : TIMER1 registers
138 #define C_MAP_GPIO_BASE 0xFFFE4800L // CS9 : GPIO registers
139 #define C_MAP_TIMER2_BASE 0xFFFE6800L // CS13 : TIMER2 registers
140 #define C_MAP_LPG_BASE 0xFFFE7800L // CS15 : LPG registers
141 #define C_MAP_PWL_BASE 0xFFFE8000L // CS16 : PWL registers
142 #define C_MAP_PWT_BASE 0xFFFE8800L // CS17 : PWT registers
143 #define C_MAP_KEYBOARD_BASE 0xFFFEB800L // CS23 : KEYBOARD registers
144 #define C_MAP_JTAG_ID_BASE 0xFFFEF000L // CS30 : JTAG ID register
145 #define C_MAP_JTAG_VERSION_BASE 0xFFFEF002L // CS30 : JTAG Version register
146 #define C_MAP_DIE_ID_CODE_BASE 0xFFFEF004L // CS30 : DIE IDENTIFICATION code registers
147 #define C_MAP_HASH_MAN_PUB_KEY_BASE 0xFFFEF00CL // CS30 : Hash of the Manufacturer Public Key registers
148 #define C_MAP_CORE_CONF_BASE 0xFFFEF01CL // CS30 : Core configuration registers
149
150
151
152 /****************************************************************************
153 * INTERNAL MEMORY MAPPING
154 ***************************************************************************/
155
156 #define C_MAP_CS6_4MBITS_BASE 0x08000000L // Main 4Mbits of Internal SRAM
157 #define C_MAP_CS6_SHD_RAM0_BASE 0x08080000L // Shared 0.5Mbits of Internal SRAM
158 #define C_MAP_CS6_SHD_RAM1_BASE 0x08090000L // Shared 0.5Mbits of Internal SRAM
159 #define C_MAP_CS6_SHD_RAM2_BASE 0x080A0000L // Shared 0.5Mbits of Internal SRAM
160
161
162
163 /****************************************************************************
164 * INTERNAL PERIPHERAL MAPPING
165 ***************************************************************************/
166
167 #define C_MAP_SHA1MD5_BASE 0x09800000L // SHA1/MD5 registers
168 #define C_MAP_DES_BASE 0x09900000L // DES/3DES registers
169 #define C_MAP_RNG_BASE 0x09A00000L // RNG registers
170 #define C_MAP_NAND_FLASH_BASE 0x09D00000L // Nand Flash Conroller registers
171 #define C_MAP_PATCH_UNIT_BASE 0x09E00000L // Patch Unit registers
172 #define C_MAP_DEBUG_UNIT_BASE 0x09F00000L // Debug Unit registers
173
174
175
176 /****************************************************************************
177 * API MAPPING
178 ***************************************************************************/
179
180 #define C_MAP_API_RAM_BASE 0xFFD00000L // API RAM address on MCU side
181 #define C_MAP_DSP_API_RAM_BASE 0xE000 // API RAM address on DSP side
182 #define C_MAP_APIC_BASE 0xFFE00000L // APIC register
183
184
185 #endif /* __SYS_MAP_H__ */
186
187 #endif /* (CHIPSET == 12) */
188