FreeCalypso > hg > tcs211-l1-reconst
comparison chipsetsw/layer1/cfile/l1_pwmgr.c @ 127:633cc67bebbc
l1_pwmgr.c: l1s_get_HWTimers_ticks() reconstructed
author | Mychaela Falconia <falcon@ivan.Harhan.ORG> |
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date | Fri, 13 May 2016 17:21:26 +0000 |
parents | c0a6b2f9723b |
children | a2f9560c1cf1 |
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126:c0a6b2f9723b | 127:633cc67bebbc |
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619 // setup time | 619 // setup time |
620 | 620 |
621 WORD32 l1s_get_HWTimers_ticks(void) | 621 WORD32 l1s_get_HWTimers_ticks(void) |
622 { | 622 { |
623 #if (CODE_VERSION != SIMULATION) | 623 #if (CODE_VERSION != SIMULATION) |
624 if (l1_config.pwr_mngt == PWR_MNGT) | |
625 { | |
626 WORD32 timer1,timer2,watchdog,HWTimer; | 624 WORD32 timer1,timer2,watchdog,HWTimer; |
627 #if (CHIPSET == 12) || (CHIPSET == 15) | 625 #if (CHIPSET == 12) || (CHIPSET == 15) |
628 WORD32 watchdog_sec; | 626 WORD32 watchdog_sec; |
629 #endif | 627 #endif |
630 UWORD16 cntlreg; | 628 UWORD16 cntlreg; |
643 #endif | 641 #endif |
644 | 642 |
645 cntlreg = Dtimer1_Get_cntlreg(); // AND 0x1F | 643 cntlreg = Dtimer1_Get_cntlreg(); // AND 0x1F |
646 if ( (cntlreg & D_TIMER_RUN) == D_TIMER_RUN) | 644 if ( (cntlreg & D_TIMER_RUN) == D_TIMER_RUN) |
647 { | 645 { |
648 cntlreg = cntlreg&0x1F; | 646 #if 0 /* match TCS211 object */ |
647 cntlreg = cntlreg&0x1F; | |
648 #endif | |
649 cntlreg >>= 2; // take PTV | 649 cntlreg >>= 2; // take PTV |
650 cntlreg = 1 << (cntlreg+1); | 650 cntlreg = 1 << (cntlreg+1); |
651 timer1 = (WORD32) ( ((Dtimer1_ReadValue()+1) * cntlreg * 0.0012308) / 4.615 ); | 651 timer1 = (WORD32) ( ((Dtimer1_ReadValue()+1) * cntlreg * 0.0012308) / 4.615 ); |
652 if (timer1 <= MIN_SLEEP_TIME) return(0); | 652 if (timer1 <= MIN_SLEEP_TIME) return(0); |
653 old = Dtimer1_ReadValue(); | 653 old = Dtimer1_ReadValue(); |
655 } | 655 } |
656 | 656 |
657 cntlreg = Dtimer2_Get_cntlreg(); | 657 cntlreg = Dtimer2_Get_cntlreg(); |
658 if ( (cntlreg & D_TIMER_RUN) == D_TIMER_RUN) | 658 if ( (cntlreg & D_TIMER_RUN) == D_TIMER_RUN) |
659 { | 659 { |
660 cntlreg = cntlreg&0x1F; | 660 #if 0 /* match TCS211 object */ |
661 cntlreg = cntlreg&0x1F; | |
662 #endif | |
661 cntlreg >>= 2; // take PTV | 663 cntlreg >>= 2; // take PTV |
662 cntlreg = 1 << (cntlreg+1); | 664 cntlreg = 1 << (cntlreg+1); |
663 timer2 = (WORD32) ( ((Dtimer2_ReadValue()+1) * cntlreg * 0.0012308) / 4.615 ); | 665 timer2 = (WORD32) ( ((Dtimer2_ReadValue()+1) * cntlreg * 0.0012308) / 4.615 ); |
664 if (timer2 <= MIN_SLEEP_TIME) return(0); | 666 if (timer2 <= MIN_SLEEP_TIME) return(0); |
665 if (HWTimer == -1) HWTimer = timer2; | 667 if (HWTimer == -1) HWTimer = timer2; |
704 } | 706 } |
705 | 707 |
706 #endif | 708 #endif |
707 | 709 |
708 return (HWTimer); | 710 return (HWTimer); |
709 } | |
710 #else // simulation part | 711 #else // simulation part |
711 return (-1); // no HW timer in simulation | 712 return (-1); // no HW timer in simulation |
712 #endif | 713 #endif |
713 return(-1); //omaps00090550 | |
714 } | 714 } |
715 | 715 |
716 #if (GSM_IDLE_RAM != 0) // Compile only if GSM_IDLE_RAM enabled | 716 #if (GSM_IDLE_RAM != 0) // Compile only if GSM_IDLE_RAM enabled |
717 | 717 |
718 void l1s_adapt_traffic_controller(void) | 718 void l1s_adapt_traffic_controller(void) |