# HG changeset patch # User Mychaela Falconia # Date 1446361433 0 # Node ID d45509318f200544cecf7faba91bfb1ff85f4f47 # Parent 68e6e5c455e0051eb9c3c5718ec0cb65ae6082dc uartfax.c: GPIO and DTR muck removed (copied from tcs211-pirelli) diff -r 68e6e5c455e0 -r d45509318f20 chipsetsw/drivers/drv_app/uart/uartfax.c --- a/chipsetsw/drivers/drv_app/uart/uartfax.c Sun Nov 01 06:54:46 2015 +0000 +++ b/chipsetsw/drivers/drv_app/uart/uartfax.c Sun Nov 01 07:03:53 2015 +0000 @@ -553,7 +553,7 @@ SYS_UWORD8 rts_level; /* RTS on RS232 side, CTS on chipset side. 1: The RS232 line is deactivated (low). */ -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) SYS_UWORD8 dtr_level; /* Controlled with an I/O on C & D-Sample and handled by Calypso+ on E-Sample. 1: The RS232 line is deactivated (low). */ @@ -915,7 +915,7 @@ * lose events detected in the RX interrupt handler. */ -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) if (call_source == 3) /* Call from Rx HISR */ dtr_level = uart->dtr_level_saved[uart->index_hisr]; else @@ -932,7 +932,7 @@ state |= ((((SYS_UWORD32) uart->rts_level) << RTS) | -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) (((SYS_UWORD32) dtr_level) << DTR) | #endif @@ -955,7 +955,7 @@ * DTR is supported on C, D & E-Sample. */ -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) state |= (((SYS_UWORD32) uart->dtr_level) << SA); #endif @@ -1965,7 +1965,7 @@ SER_restart_uart_sleep_timer (); uart_sleep_timer_enabled = 1; -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) uart->index_hisr = (uart->index_hisr + 1) & 0x01; /* 0 or 1 */ #endif @@ -2166,7 +2166,7 @@ (uart->rd_call_setup == rm_reInstall))) { if ((bytes_in_rx_buffer >= uart->rx_threshold_level) || -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) uart->dtr_change_detected[uart->index_hisr] || #endif uart->break_received || @@ -2179,7 +2179,7 @@ uart->reading_suspended = 0; uart->break_received = 0; uart->esc_seq_received = 0; -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) uart->dtr_change_detected[uart->index_hisr] = 0; #endif } @@ -2592,7 +2592,7 @@ else { uart->tx_stopped_by_driver = 0; - LowGPIO(1); + /* LowGPIO(1); */ #if ((CHIPSET != 5) && (CHIPSET != 6)) /* @@ -2999,7 +2999,7 @@ else uart->rts_level = 1; -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) /* * On C & D-Sample, 2 I/O are used to control DCD and DTR on UART Modem. * DCD: I/O 2 (output) @@ -3219,7 +3219,7 @@ WRITE_UART_REGISTER (uart, IER, 0x00); -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) AI_MaskIT (ARMIO_MASKIT_GPIO); #elif (CHIPSET == 12) DISABLE_DSR_INTERRUPT (uart); @@ -3360,7 +3360,7 @@ else uart->rts_level = 1; -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) /* * Read the state of DTR and select the edge. */ @@ -4322,8 +4322,10 @@ /* If we have been stopped due to high RTS, we have to * wake up application processor by IRQ via IO1 -HW */ +#if 0 if (uart->tx_stopped_by_driver) HighGPIO(1); +#endif /* * If: @@ -4544,7 +4546,7 @@ *state |= ((((SYS_UWORD32) uart->rts_level) << RTS) | -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) (((SYS_UWORD32) uart->dtr_level) << DTR) | #endif @@ -4568,7 +4570,7 @@ * DTR is supported on C, D & E-Sample. */ -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) *state |= (((SYS_UWORD32) uart->dtr_level) << SA); #endif @@ -4639,7 +4641,7 @@ * DSR is not supported on all platforms. */ -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) if (mask & (1 << SA)) #else if ((mask & (1 << SA)) || (mask & (1 << DCD))) @@ -4741,7 +4743,7 @@ * The DCD field is ignored if the SB bit of the mask is set. */ -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) if (!(mask & (1 << SB)) && (mask & (1 << DCD))) { @@ -4777,7 +4779,7 @@ * DCD is supported on C, D & E-Sample. */ -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) if (mask & (1 << SB)) { @@ -4883,7 +4885,7 @@ case RX_DATA: -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) uart->index_it = (uart->index_it + 1) & 0x01; /* 0 or 1 */ uart->dtr_change_detected[uart->index_it] = 0; uart->dtr_level_saved[uart->index_it] = uart->dtr_level; @@ -5017,7 +5019,7 @@ return (result); } -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) +#if 0 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) /******************************************************************************* * * UAF_DTRInterruptHandler