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comparison chipsetsw/system/bootloader/src/bootloader.s @ 0:509db1a7b7b8

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initial import: leo2moko-r1
author Space Falcon <falcon@ivan.Harhan.ORG>
date Mon, 01 Jun 2015 03:24:05 +0000
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-1:000000000000 0:509db1a7b7b8
1 ;/******************************************************************************
2 ; *
3 ; * BOOTLOADER.S
4 ; *
5 ; * This module initializes the system stack for the bootloader and calls the bootloader.
6 ; * If the bootloader starts the function INT_Initialize is called.
7 ; *
8 ; * (C) Texas Instruments 1999
9 ; *
10 ; *****************************************************************************/
11
12 ;
13 ;/* Define constants used in low-level initialization. */
14 ;
15
16 LOCKOUT .equ 00C0h ; Interrupt lockout value
17 MODE_MASK .equ 001Fh ; Processor Mode Mask
18 SUP_MODE .equ 0013h ; Supervisor Mode (SVC)
19
20 SYSTEM_SIZE .equ 1024 ; Define the system stack size
21
22 .ref _sta_select_application
23 .ref _INT_Initialize
24
25 .ref end ; Ending address of BSS section
26
27
28 .sect ".text"
29
30 .def _INT_Bootloader_Start
31
32
33
34 addrCS0 .word 0xfffffb00 ;CS0 address space
35
36
37 .if BOARD = 6 ; EVA4
38 .if CHIPSET != 12
39 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
40 CS1_MEM_REG .short 0x281 ; 1 Dummy Cycle 8 bit 1 WS SW BP enable
41 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
42 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
43 CS4_MEM_REG .short 0xe85 ; default reset value
44 .endif
45
46 .if CHIPSET = 3
47 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
48
49 .elseif CHIPSET = 4
50 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
51 CS7_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
52
53 .elseif CHIPSET = 5
54 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
55
56 .elseif CHIPSET = 6
57 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
58
59 .elseif CHIPSET = 7
60 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
61 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM - 0 WS, 32 bits, little, write disable
62
63 .elseif CHIPSET = 8
64 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
65 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM - 0 WS, 32 bits, little, write disable
66
67 .elseif CHIPSET = 10
68 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
69 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM - 0 WS, 32 bits, little, write disable
70
71 .elseif CHIPSET = 11
72 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
73 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM - 0 WS, 32 bits, little, write disable
74
75 .elseif CHIPSET = 12
76 CS0_MEM_REG .short 0x2a1 ; CALYPSO PLUS TEST MODE - TO BE ERASED - 1 Dummy Cycle 16 bit 1 WS SW BP enable
77 CS4_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
78 CS5_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
79 .endif
80
81 .elseif BOARD = 7 ; B-Sample
82 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
83 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
84 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
85 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
86 CS4_MEM_REG .short 0x281 ; 1 Dummy Cycle 8 bit 1 WS SW BP enable
87
88 .if CHIPSET = 3
89 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
90
91 .elseif CHIPSET = 4
92 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
93 CS7_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
94
95 .elseif CHIPSET = 5
96 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
97
98 .elseif CHIPSET = 6
99 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
100
101 .endif
102
103 .elseif BOARD = 8 ; C-Sample SRAM CS0
104 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 0 WS SW BP enable
105 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
106 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
107 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
108 CS4_MEM_REG .short 0x281 ; 1 Dummy Cycle 8 bit 1 WS SW BP enable
109
110 .if CHIPSET = 4
111 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
112 CS7_MEM_REG .short 0x0c0 ;Internal RAM init : 0 WS, 32 bits, little, write enable
113
114 .elseif CHIPSET = 7
115 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
116 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
117
118 .elseif CHIPSET = 8
119 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
120 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
121 .endif
122
123 .elseif BOARD = 9 ; C-Sample FLASH CS0
124 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
125 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
126 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
127 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
128 CS4_MEM_REG .short 0x281 ; 1 Dummy Cycle 8 bit 1 WS SW BP enable
129
130 .if CHIPSET = 4
131 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
132 CS7_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable
133
134 .elseif CHIPSET = 7
135 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
136 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
137
138 .elseif CHIPSET = 8
139 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
140 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
141 .endif
142
143 .elseif BOARD = 40 ; D-Sample SRAM CS0
144 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
145 CS1_MEM_REG .short 0x2a3 ; 1 Dummy Cycle 16 bit 3 WS SW BP enable
146 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
147 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
148 CS4_MEM_REG .short 0x281 ; 1 Dummy Cycle 8 bit 1 WS SW BP enable
149
150 .if CHIPSET = 8
151 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
152 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
153
154 .elseif CHIPSET = 10
155 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
156 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
157
158 .elseif CHIPSET = 11
159 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
160 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
161 .endif
162
163 .elseif BOARD = 41 ; D-Sample FLASH CS0
164 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
165 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
166 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
167 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
168 CS4_MEM_REG .short 0x281 ; 1 Dummy Cycle 8 bit 1 WS SW BP enable
169
170 .if CHIPSET = 8
171 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
172 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
173
174 .elseif CHIPSET = 10
175 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
176 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
177
178 .elseif CHIPSET = 11
179 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
180 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
181 .endif
182
183 .elseif BOARD = 43 ; E-Sample - FLASH
184 .if CHIPSET != 12
185 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
186 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
187 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
188 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
189 CS4_MEM_REG .short 0x281 ; 1 Dummy Cycle 8 bit 1 WS SW BP enable
190
191 .else
192 CS0_MEM_REG .short 0x2a1 ; CALYPSO PLUS TEST MODE BOARD 43 - TO BE ERASED - 1 Dummy Cycle 16 bit 1 WS SW BP enable
193 CS4_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
194 CS5_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
195 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
196 .endif ; CHIPSET = 12
197
198 .elseif BOARD = 45 ; EVA_CONSO - FLASH
199
200 .if CHIPSET != 12
201 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
202 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
203 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
204 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
205 CS4_MEM_REG .short 0x281 ; 1 Dummy Cycle 8 bit 1 WS SW BP enable
206 .else
207 CS0_MEM_REG .short 0x2a1 ; CALYPSO PLUS TEST MODE BOARD 43 - TO BE ERASED - 1 Dummy Cycle 16 bit 1 WS SW BP enable
208 CS4_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
209 CS5_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
210 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
211 .endif ; CHIPSET = 12
212 .endif ; BOARD = 6 or 7 or 8 or 9 or 40 or 41 or 43 or 45
213
214
215 CTL_MEM_REG .short 0x02a ; rhea strobe 0/1 + API access size adaptation
216
217 .if CHIPSET = 4
218 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
219 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
220 RHEA_CNTL_REG .word 0xFFFFF900 ; RHEA control register address
221
222 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
223 ; Use DPLL, Divide by 1
224 DPLL_CONTROL_RST .short 0x2006 ; Configure DPLL in default state
225 RHEA_CONTROL_RST .short 0xFF22 ; Set access factor in order to access the DPLL register
226 ; independently of the ARM clock
227
228 .elseif CHIPSET = 6
229 ;
230 ; Constants to configure ULYSSE G1 with VTCXO at 26MHz
231 ;
232 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
233 CNTLCLK_26MHZ_SELECTOR .short 0x0040 ; VTCXO_26 selector
234
235 .elseif CHIPSET = 7
236 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
237 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
238 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
239 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
240
241 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
242 ; Use DPLL, Divide by 1
243 DPLL_CONTROL_RST .short 0x2006 ; Configure DPLL in default state
244 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
245 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
246
247 .elseif CHIPSET = 8
248 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
249 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
250 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
251 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
252
253 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
254 ; Use DPLL, Divide by 1
255 DPLL_CONTROL_RST .short 0x2006 ; Configure DPLL in default state
256 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
257 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
258
259 .elseif CHIPSET = 10
260 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
261 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
262 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
263 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
264
265 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
266 ; Use DPLL, Divide by 1
267 DPLL_CONTROL_RST .short 0x2006 ; Configure DPLL in default state
268 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
269 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
270
271 .elseif CHIPSET = 11
272 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
273 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
274 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
275 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
276
277 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
278 ; Use DPLL, Divide by 1
279 DPLL_CONTROL_RST .short 0x2006 ; Configure DPLL in default state
280 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
281 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
282
283 .elseif CHIPSET = 12
284 DBG_DMA_P2 .word 0xFFFEF02C ; DBG_DMA_P2 register address
285 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
286 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
287 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
288 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
289
290 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
291 ; Use DPLL, Divide by 1
292 DPLL_CONTROL_RST .short 0x2006 ; Configure DPLL in default state
293 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
294 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
295 DBG_DMA_P2_RST .short 0x0002 ; DBG_DMA_P2 register reset value - GPO2 replaces ADD24
296
297 .endif ; CHIPSET = 4 or 6 or 7 or 8 or 10 or 11 or 12
298
299 CLKM_MEM_REG .equ 0x31 ;the same define INIT_CLKM_ARM_CLK = 0x1031 for InitArmAfterReset
300
301
302 _INT_Bootloader_Start
303
304 ;
305 ; Basic initializations
306 ;
307
308 ;
309 ; Configuration of ARM clock and DPLL frequency
310 ;
311 .if CHIPSET = 4
312 ;
313 ; Configure RHEA access factor in order to allow the access of DPLL register
314 ;
315 ldr r1,RHEA_CNTL_REG ; Load address of RHEA control register in R1
316 ldrh r2,RHEA_CONTROL_RST ; Load RHEA configuration value in R2
317 strh r2,[r1] ; Store DPLL reset value in RHEA control register
318
319 ;
320 ; Configure DPLL register with reset value
321 ;
322 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
323 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
324 strh r2,[r1] ; Store DPLL reset value in DPLL register
325
326 ;
327 ; Wait that DPLL goes in BYPASS mode
328 ;
329 Wait_DPLL_Bypass
330 ldr r2,[r1] ; Load DPLL register
331 and r2,r2,#1 ; Perform a mask on bit 0
332 cmp r2,#1 ; Compare DPLL lock bit
333 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
334
335 ;
336 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
337 ; generate ARM clock with division factor of 1.
338 ;
339 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
340 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
341 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
342
343 .elseif CHIPSET = 6
344 ;
345 ; Setting of VTCXO_26MHZ bit to '1' in order to divide reference clock for peripherals.
346 ; This setting is required on ULYSSE G1 with a VTCXO clock to 26MHz.
347 ;
348 ldr r1,CNTL_ARM_CLK_REG ; Load CLKM base register address in R1
349 ldrh r2,[r1,#2] ; Load contents of CNTL_CLK register in R2
350 ldr r0,CNTLCLK_26MHZ_SELECTOR ; Load configuration of 26MHz selector
351 orr r0,r0,r2
352 strh r0,[r1,#2]
353
354 .elseif CHIPSET = 7
355 ;
356 ; Configure DPLL register with reset value
357 ;
358 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
359 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
360 strh r2,[r1] ; Store DPLL reset value in DPLL register
361
362 ;
363 ; Wait that DPLL goes in BYPASS mode
364 ;
365 Wait_DPLL_Bypass
366 ldr r2,[r1] ; Load DPLL register
367 and r2,r2,#1 ; Perform a mask on bit 0
368 cmp r2,#1 ; Compare DPLL lock bit
369 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
370
371 ;
372 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
373 ; generate ARM clock with division factor of 1.
374 ;
375 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
376 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
377 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
378
379 ;
380 ; Disable the DU module by setting bit 11 to '1'
381 ;
382 ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF
383 ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
384 ldrh r0,[r1] ; Load Extra Control register CONF in r0
385 orr r0,r0,r2 ; Disable DU module
386 strh r0,[r1] ; Store configuration in Extra Control register CONF
387
388 ;
389 ; Disable all MPU protections
390 ;
391 ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register
392 ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register
393 strh r2,[r1] ; Store reset value of MPU_CTL register
394
395 .elseif CHIPSET = 8
396 ;
397 ; Configure DPLL register with reset value
398 ;
399 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
400 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
401 strh r2,[r1] ; Store DPLL reset value in DPLL register
402
403 ;
404 ; Wait that DPLL goes in BYPASS mode
405 ;
406 Wait_DPLL_Bypass
407 ldr r2,[r1] ; Load DPLL register
408 and r2,r2,#1 ; Perform a mask on bit 0
409 cmp r2,#1 ; Compare DPLL lock bit
410 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
411
412 ;
413 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
414 ; generate ARM clock with division factor of 1.
415 ;
416 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
417 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
418 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
419
420 ;
421 ; Disable the DU module by setting bit 11 to '1'
422 ;
423 ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF
424 ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
425 ldrh r0,[r1] ; Load Extra Control register CONF in r0
426 orr r0,r0,r2 ; Disable DU module
427 strh r0,[r1] ; Store configuration in Extra Control register CONF
428
429 ;
430 ; Disable all MPU protections
431 ;
432 ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register
433 ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register
434 strh r2,[r1] ; Store reset value of MPU_CTL register
435
436
437 .elseif CHIPSET = 10
438 ;
439 ; Configure DPLL register with reset value
440 ;
441 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
442 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
443 strh r2,[r1] ; Store DPLL reset value in DPLL register
444
445 ;
446 ; Wait that DPLL goes in BYPASS mode
447 ;
448 Wait_DPLL_Bypass
449 ldr r2,[r1] ; Load DPLL register
450 and r2,r2,#1 ; Perform a mask on bit 0
451 cmp r2,#1 ; Compare DPLL lock bit
452 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
453
454 ;
455 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
456 ; generate ARM clock with division factor of 1.
457 ;
458 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
459 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
460 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
461
462 ;
463 ; Disable the DU module by setting bit 11 to '1'
464 ;
465 ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF
466 ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
467 ldrh r0,[r1] ; Load Extra Control register CONF in r0
468 orr r0,r0,r2 ; Disable DU module
469 strh r0,[r1] ; Store configuration in Extra Control register CONF
470
471 ;
472 ; Disable all MPU protections
473 ;
474 ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register
475 ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register
476 strh r2,[r1] ; Store reset value of MPU_CTL register
477
478 .elseif CHIPSET = 11
479 ;
480 ; Configure DPLL register with reset value
481 ;
482 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
483 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
484 strh r2,[r1] ; Store DPLL reset value in DPLL register
485
486 ;
487 ; Wait that DPLL goes in BYPASS mode
488 ;
489 Wait_DPLL_Bypass
490 ldr r2,[r1] ; Load DPLL register
491 and r2,r2,#1 ; Perform a mask on bit 0
492 cmp r2,#1 ; Compare DPLL lock bit
493 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
494
495 ;
496 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
497 ; generate ARM clock with division factor of 1.
498 ;
499 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
500 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
501 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
502
503 ;
504 ; Disable the DU module by setting bit 11 to '1'
505 ;
506 ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF
507 ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
508 ldrh r0,[r1] ; Load Extra Control register CONF in r0
509 orr r0,r0,r2 ; Disable DU module
510 strh r0,[r1] ; Store configuration in Extra Control register CONF
511
512 ;
513 ; Disable all MPU protections
514 ;
515 ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register
516 ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register
517 strh r2,[r1] ; Store reset value of MPU_CTL register
518
519 .elseif CHIPSET = 12
520 .if BOARD = 6
521 ; Configure DBG_DMA_P2 reg => GPO_2 output pin for EVA4
522 ldr r1,DBG_DMA_P2 ; Load address of DBG_DMA_P2 register in R1
523 ldrh r2,DBG_DMA_P2_RST ; Load DBG_DMA_P2 reset value in R2
524 strh r2,[r1] ; Store reset value in register
525 ;
526 .endif ; BOARD = 6
527 ;
528 ; Configure DPLL register with reset value
529 ;
530 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
531 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
532 strh r2,[r1] ; Store DPLL reset value in DPLL register
533
534 ;
535 ; Wait that DPLL goes in BYPASS mode
536 ;
537 Wait_DPLL_Bypass
538 ldr r2,[r1] ; Load DPLL register
539 and r2,r2,#1 ; Perform a mask on bit 0
540 cmp r2,#1 ; Compare DPLL lock bit
541 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
542
543 ;
544 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
545 ; generate ARM clock with division factor of 1.
546 ;
547 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
548 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
549 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
550
551 ;
552 ; Disable the DU module by setting bit 11 to '1'
553 ;
554 ; ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF
555 ; ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
556 ; ldrh r0,[r1] ; Load Extra Control register CONF in r0
557 ; orr r0,r0,r2 ; Disable DU module
558 ; strh r0,[r1] ; Store configuration in Extra Control register CONF
559
560 ;
561 ; Disable all MPU protections
562 ;
563 ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register
564 ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register
565 strh r2,[r1] ; Store reset value of MPU_CTL register
566
567 .endif ; CHIPSET = 4 or 6 or 7 or 8 or 10 or 11 or 12
568
569 ldr r1,addrCS0
570
571 .if CHIPSET = 12
572 ldrh r2,CS0_MEM_REG ; CALYPSO PLUS TEST MODE - TO BE ERASED - ROM initialization
573 strh r2,[r1, #0x00] ; CS5
574
575 ldrh r2,CS5_MEM_REG ; ROM initialization
576 strh r2,[r1, #0x0A] ; CS5
577
578 ldrh r2,CS4_MEM_REG ; RAM Initialization
579 strh r2,[r1,#0x08] ; CS4
580
581 .else
582 ldrh r2,CS0_MEM_REG ; ROM initialization
583 strh r2,[r1] ; CS0
584
585 ldrh r2,CS1_MEM_REG ; RAM Initialization
586 strh r2,[r1,#2] ; CS1
587
588 ldrh r2,CS2_MEM_REG ; RAM Initialization
589 strh r2,[r1,#4] ; CS2
590
591 ldrh r2,CS3_MEM_REG ; parallel I/O
592 strh r2,[r1,#6] ; CS3
593
594 ldrh r2,CS4_MEM_REG ; Debug Latch
595 strh r2,[r1,#0xa] ; CS4
596 .endif
597
598 .if CHIPSET = 3
599 ldrh r2,CS6_MEM_REG ; Ulysse/G0 Internal SRAM initialization
600 strh r2,[r1,#0xc] ; CS6
601
602 .elseif CHIPSET = 4
603 ldrh r2,CS6_MEM_REG ; Samson Internal SRAM initialization
604 strh r2,[r1,#0xc] ; CS6
605
606 ldrh r2,CS7_MEM_REG ; Internal Boot RAM
607 strh r2,[r1,#0x8] ; CS7
608
609 .elseif CHIPSET = 5
610 ldrh r2,CS6_MEM_REG ; Ulysse/G1 Internal SRAM initialization
611 strh r2,[r1,#0xc] ; CS6
612
613 .elseif CHIPSET = 6
614 ldrh r2,CS6_MEM_REG ; Ulysse/G1 Internal SRAM initialization
615 strh r2,[r1,#0xc] ; CS6
616
617 .elseif CHIPSET = 7
618 ldrh r2,CS6_MEM_REG ; Calypso/G2 Internal SRAM initialization
619 strh r2,[r1,#0xc] ; CS6
620
621 ldrh r2,CS7_MEM_REG ; Internal Boot ROM initialization
622 strh r2,[r1,#0x8] ; CS7
623
624 .elseif CHIPSET = 8
625 ldrh r2,CS6_MEM_REG ; Calypso/G2 Internal SRAM initialization
626 strh r2,[r1,#0xc] ; CS6
627
628 ldrh r2,CS7_MEM_REG ; Internal Boot ROM initialization
629 strh r2,[r1,#0x8] ; CS7
630
631 .elseif CHIPSET = 10
632 ldrh r2,CS6_MEM_REG ; Calypso/G2 Internal SRAM initialization
633 strh r2,[r1,#0xc] ; CS6
634
635 ldrh r2,CS7_MEM_REG ; Internal Boot ROM initialization
636 strh r2,[r1,#0x8] ; CS7
637
638 .elseif CHIPSET = 11
639 ldrh r2,CS6_MEM_REG ; Calypso/G2 Internal SRAM initialization
640 strh r2,[r1,#0xc] ; CS6
641
642 ldrh r2,CS7_MEM_REG ; Internal Boot ROM initialization
643 strh r2,[r1,#0x8] ; CS7
644
645 .endif ; CHIPSET = 3 or 4 or 5 or 6 or 7 or 8 or 10 or 11
646
647 ldrh r2,CTL_MEM_REG ; API-RHEA configuration
648 strh r2,[r1,#0xe]
649
650 ; Initialize the system stack to allow to use the bootloader.
651
652 LDR a1,BSS_End ; Pickup the ending address of BSS
653 MOV a2,#SYSTEM_SIZE ; Pickup system stack size
654 SUB a2,a2,#4 ; Subtract one word for first addr
655 ADD a3,a1,a2 ; Build start of system stack area
656 BIC a3,a3,#3 ; Insure word aligment of stack
657 MOV sp,a3 ; Setup initial stack pointer
658
659
660 ; Call the function which allows to select the bootloader or the user's
661 ; application.
662
663 STMFD sp!, {a1-a4,R12}
664 BL _sta_select_application
665 LDMFD sp!, {a1-a4,R12}
666
667 B _INT_Initialize
668
669 ; /* Define all the global addresses used in this section */
670
671 BSS_End
672 .word end
673
674 .end
675