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comparison chipsetsw/drivers/drv_core/inth/inth.h @ 0:509db1a7b7b8

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initial import: leo2moko-r1
author Space Falcon <falcon@ivan.Harhan.ORG>
date Mon, 01 Jun 2015 03:24:05 +0000
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-1:000000000000 0:509db1a7b7b8
1 /*******************************************************************************
2 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
3
4 Property of Texas Instruments -- For Unrestricted Internal Use Only
5 Unauthorized reproduction and/or distribution is strictly prohibited. This
6 product is protected under copyright law and trade secret law as an
7 unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All
8 rights reserved.
9
10
11 Filename : inth.h
12
13 Description : Header file for the INTH module
14
15 Project : drivers
16
17 Author : pmonteil@tif.ti.com Patrice Monteil.
18
19 Version number : 1.17
20
21 Date : 09/02/03
22
23 Previous delta : 01/22/01 10:32:33
24
25 SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/RELEASE_GPRS/drivers1/common/SCCS/s.inth.h
26
27 Sccs Id (SID) : '@(#) inth.h 1.10 01/30/01 10:22:23 '
28
29
30 *****************************************************************************/
31
32 #include "l1sw.cfg"
33 #include "chipset.cfg"
34
35 #if (CHIPSET != 12)
36
37 #if (OP_L1_STANDALONE == 0)
38 #include "main/sys_types.h"
39 #else
40 #include "sys_types.h"
41 #endif
42
43 /* Adress of the registers */
44
45 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9)|| (CHIPSET == 10) || (CHIPSET == 11))
46 #define INTH_IT_REG1 MEM_INTH_ADDR /* INTH IT register 1 */
47 #define INTH_IT_REG2 (MEM_INTH_ADDR + 0x02) /* INTH IT register 2 */
48 #define INTH_MASK_REG1 (MEM_INTH_ADDR + 0x08) /* INTH mask register 1 */
49 #define INTH_MASK_REG2 (MEM_INTH_ADDR + 0x0a) /* INTH mask register 2 */
50 #define INTH_B_IRQ_REG (MEM_INTH_ADDR + 0x10) /* INTH source binary IRQ reg. */
51 #define INTH_B_FIQ_REG (MEM_INTH_ADDR + 0x12) /* INTH source binary FIQ reg. */
52 #define INTH_CTRL_REG (MEM_INTH_ADDR + 0x14) /* INTH control register */
53 #define INTH_EXT_REG (MEM_INTH_ADDR + 0x20) /* INTH 1st external int. reg. */
54 #else
55 #define INTH_IT_REG MEM_INTH_ADDR /* INTH IT register */
56 #define INTH_MASK_REG (MEM_INTH_ADDR + 0x02) /* INTH mask register */
57 #define INTH_S_IRQ_REG (MEM_INTH_ADDR + 0x04) /* INTH source IRQ register */
58 #define INTH_S_FIQ_REG (MEM_INTH_ADDR + 0x06) /* INTH source FIQ register */
59 #define INTH_B_IRQ_REG (MEM_INTH_ADDR + 0x08) /* INTH source binary IRQ reg. */
60 #define INTH_B_FIQ_REG (MEM_INTH_ADDR + 0x0a) /* INTH source binary FIQ reg. */
61 #define INTH_CTRL_REG (MEM_INTH_ADDR + 0x0c) /* INTH control register */
62 #define INTH_EXT_REG (MEM_INTH_ADDR + 0x0e) /* INTH 1st external int. reg. */
63 #endif
64
65 /* Interrupts number */
66
67 #define INTH_TIMER 0 /* number of the TIMER int. */
68 #define INTH_AIRQ_FIRST 1 /* first external int. number */
69 #define INTH_AIRQ_LAST 13 /* last external int. number */
70 #define INTH_DMA 14 /* number of the DMA int. */
71 #define INTH_LEAD 15 /* number of the LEAD int. */
72
73 /* Bit definition of INTH interrupt level registers */
74
75 #define INTH_FIQ_NIRQ 0x0001
76 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11))
77 #define INTH_PRIORITY 0x007c
78 #define INTH_EDGE_NLVL 0x0002
79 #else
80 #define INTH_PRIORITY 0x001e
81 #define INTH_EDGE_NLVL 0x0020
82 #endif
83
84
85 /* Bit definition of INTH source binary registers */
86
87 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11))
88 #define INTH_SRC_NUM 0x001f
89 #else
90 #define INTH_SRC_NUM 0x000f
91 #endif
92
93
94 /* Bit definition of INTH Control Register */
95
96 #define INTH_NEW_IRQ_AGR 0x0001
97 #define INTH_NEW_FIQ_AGR 0x0002
98
99 /* Other useful constants */
100
101 #define INTH_IRQ 0
102 #define INTH_FIQ 1
103 #define INTH_LEVEL 0
104 #define INTH_EDGE 1
105
106 /*
107 * Macros
108 */
109
110 #define INT_MASK(interrupt) (1 << (interrupt - 1))
111 #define PENDING_INT(pendingITs, interrupt) (pendingITs & INT_MASK(interrupt))
112
113 /*--------------------------------------------------------------*/
114 /* INTH_ENABLEONEIT() */
115 /*--------------------------------------------------------------*/
116 /* Parameters : num of the IT to enable */
117 /* Return : none */
118 /* Functionality : Unmask one it */
119 /*--------------------------------------------------------------*/
120 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11))
121 #define INTH_ENABLEONEIT(it)( \
122 (it < 16) ? (* (volatile unsigned short *) INTH_MASK_REG1 &= ~(1 << it)) : \
123 (* (volatile unsigned short *) INTH_MASK_REG2 &= ~(1 << (it-16))) \
124 )
125 #else
126 #define INTH_ENABLEONEIT(it)(* (volatile unsigned short *) INTH_MASK_REG &= ~(1 << it))
127 #endif
128
129 /*--------------------------------------------------------------*/
130 /* INTH_DISABLEONEIT() */
131 /*--------------------------------------------------------------*/
132 /* Parameters : num of the IT to disable */
133 /* Return : none */
134 /* Functionality : mask one it */
135 /*--------------------------------------------------------------*/
136 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11))
137 #define INTH_DISABLEONEIT(it)( \
138 (it < 16) ? (* (volatile unsigned short *) INTH_MASK_REG1 |= (1 << it)) : \
139 (* (volatile unsigned short *) INTH_MASK_REG2 |= (1 << (it-16))) \
140 )
141 #else
142 #define INTH_DISABLEONEIT(it)(* (volatile unsigned short *) INTH_MASK_REG |= (1 << it))
143 #endif
144
145 /*--------------------------------------------------------------*/
146 /* INTH_ENABLEALLIT() */
147 /*--------------------------------------------------------------*/
148 /* Parameters : none */
149 /* Return : none */
150 /* Functionality : Enable all it */
151 /*--------------------------------------------------------------*/
152
153 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11))
154 #define INTH_ENABLEALLIT { \
155 * (volatile unsigned short *) INTH_MASK_REG1 = 0x0000; \
156 * (volatile unsigned short *) INTH_MASK_REG2 = 0x0000; \
157 }
158 #else
159 #define INTH_ENABLEALLIT ( * (volatile unsigned short *) INTH_MASK_REG = 0x0000)
160 #endif
161
162 /*--------------------------------------------------------------*/
163 /* INTH_DISABLEALLIT() */
164 /*--------------------------------------------------------------*/
165 /* Parameters : none */
166 /* Return : none */
167 /* Functionality :mask all it */
168 /*--------------------------------------------------------------*/
169
170 #if (CHIPSET == 4)
171 #define INTH_DISABLEALLIT { \
172 * (volatile unsigned short *) INTH_MASK_REG1 = 0xffff; \
173 * (volatile unsigned short *) INTH_MASK_REG2 = 0x000f; \
174 }
175 #elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 9))
176 #define INTH_DISABLEALLIT { \
177 * (volatile unsigned short *) INTH_MASK_REG1 = 0xffff; \
178 * (volatile unsigned short *) INTH_MASK_REG2 = 0x01ff; \
179 }
180 #elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)
181 #define INTH_DISABLEALLIT { \
182 * (volatile unsigned short *) INTH_MASK_REG1 = 0xffff; \
183 * (volatile unsigned short *) INTH_MASK_REG2 = 0xffff; \
184 }
185 #else
186 #define INTH_DISABLEALLIT (* (volatile unsigned short *) INTH_MASK_REG = 0xffff)
187 #endif
188
189
190 /*--------------------------------------------------------------*/
191 /* INTH_CLEAR() */
192 /*--------------------------------------------------------------*/
193 /* Parameters : value to write */
194 /* Return : none */
195 /* Functionality :valid next it */
196 /*--------------------------------------------------------------*/
197
198
199 #define INTH_CLEAR (* (volatile SYS_UWORD16 *) INTH_CTRL_REG = 0x0003)
200
201
202 /*--------------------------------------------------------------*/
203 /* INTH_VALIDNEXT() */
204 /*--------------------------------------------------------------*/
205 /* Parameters : num of the processed it */
206 /* Return : none */
207 /* Functionality :valid next it */
208 /*--------------------------------------------------------------*/
209
210 #define INTH_VALIDNEXT (intARM)( * (volatile SYS_UWORD16 *) INTH_CTRL_REG |= (1 << intARM))
211
212 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11))
213 /*--------------------------------------------------------------*/
214 /* INTH_RESETALLIT() */
215 /*--------------------------------------------------------------*/
216 /* Parameters : None */
217 /* Return : None */
218 /* Functionality :Reset the inth it register */
219 /*--------------------------------------------------------------*/
220
221 #define INTH_RESETALLIT { \
222 * (volatile unsigned short *) INTH_IT_REG1 &= 0x0000; \
223 * (volatile unsigned short *) INTH_IT_REG2 &= 0x0000; \
224 }
225 #endif
226
227
228 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11))
229 /*-------------------------------------------------------------*/
230 /* INTH_RESETONEIT() */
231 /*-------------------------------------------------------------*/
232 /* Parameters : Num of the IT to reset */
233 /* Return : None */
234 /* Functionality : Reset one IT of the inth IT register */
235 /*-------------------------------------------------------------*/
236 #define INTH_RESETONEIT(it) ( \
237 (it<16) ? (* (volatile unsigned short *) INTH_IT_REG1 &= ~(1 << it)) : \
238 (* (volatile unsigned short *) INTH_IT_REG2 &= ~(1 << (it-16))) \
239 )
240 #else // CHIPSET == 2,3
241 #define INTH_RESETONEIT(it) (* (volatile unsigned short *) INTH_IT_REG &= ~(1 << it))
242 #endif // CHIPSET
243
244 /* Prototypes */
245
246 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11))
247 unsigned long INTH_GetPending (void);
248 unsigned long INTH_ResetIT (void);
249 #else
250 unsigned short INTH_GetPending (void);
251 unsigned short INTH_ResetIT (void);
252 #endif
253
254 unsigned short INTH_Ack (int);
255 void INTH_InitLevel (int, int, int, int);
256
257
258 #endif /* endif chipset != 12 */
259