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comparison chipsetsw/drivers/drv_core/conf/sys_conf.h @ 0:509db1a7b7b8

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initial import: leo2moko-r1
author Space Falcon <falcon@ivan.Harhan.ORG>
date Mon, 01 Jun 2015 03:24:05 +0000
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1 /* @(#) nom : sys_conf.h SID: 1.3 date : 05/23/03 */
2 /* Filename: sys_conf.h */
3 /* Version: 1.3 */
4 /******************************************************************************
5 * WIRELESS COMMUNICATION SYSTEM DEVELOPMENT
6 *
7 * (C) 2002 Texas Instruments France. All rights reserved
8 *
9 * Author : Francois AMAND
10 *
11 *
12 * Important Note
13 * --------------
14 *
15 * This S/W is a preliminary version. It contains information on a product
16 * under development and is issued for evaluation purposes only. Features
17 * characteristics, data and other information are subject to change.
18 *
19 * The S/W is furnished under Non Disclosure Agreement and may be used or
20 * copied only in accordance with the terms of the agreement. It is an offence
21 * to copy the software in any way except as specifically set out in the
22 * agreement. No part of this document may be reproduced or transmitted in any
23 * form or by any means, electronic or mechanical, including photocopying and
24 * recording, for any purpose without the express written permission of Texas
25 * Instruments Inc.
26 *
27 ******************************************************************************
28 *
29 * FILE NAME: sys_conf.h
30 *
31 *
32 * PURPOSE: Include file to configure CONF CORE module of CALYPSO PLUS.
33 *
34 *
35 * FILE REFERENCES:
36 *
37 * Name IO Description
38 * ------------- -- ---------------------------------------------
39 *
40 *
41 *
42 * EXTERNAL VARIABLES:
43 *
44 * Source:
45 *
46 * Name Type IO Description
47 * ------------- --------------- -- ------------------------------
48 *
49 *
50 *
51 * EXTERNAL REFERENCES:
52 *
53 * Name Description
54 * ------------------ -------------------------------------------------------
55 *
56 *
57 *
58 * ABNORMAL TERMINATION CONDITIONS, ERROR AND WARNING MESSAGES:
59 *
60 *
61 *
62 * ASSUMPTION, CONSTRAINTS, RESTRICTIONS:
63 *
64 *
65 *
66 * NOTES:
67 *
68 *
69 *
70 * REQUIREMENTS/FUNCTIONAL SPECIFICATION REFERENCES:
71 *
72 *
73 *
74 *
75 * DEVELOPMENT HISTORY:
76 *
77 * Date Name(s) Version Description
78 * ----------- -------------- ------- -------------------------------------
79 * 11-Oct-2002 Francois AMAND 0.0.1 First implementation
80 *
81 * ALGORITHM:
82 *
83 *
84 *****************************************************************************/
85
86 #ifndef __SYS_CONF_H__
87 #define __SYS_CONF_H__
88
89 #include "l1sw.cfg"
90 #include "chipset.cfg"
91
92 #if (CHIPSET == 12)
93 #if (OP_L1_STANDALONE == 0)
94 #include "main/sys_types.h"
95 #else
96 #include "sys_types.h"
97 #endif
98
99 #include "sys_map.h"
100 #include "sys_conf_dsp_int.h"
101
102
103 /****************************************************************************
104 * CONSTANT DEFINITION
105 ***************************************************************************/
106
107 /*
108 * Registers offset definition
109 */
110 #define C_CONF_CORE_OFFSET 0x00
111 #define C_CONF_PULL_PWRDN_OFFSET 0x06
112
113 #define C_DBG_CORE1_OFFSET 0x02
114 #define C_DBG_CORE2_OFFSET 0x04
115
116 #define C_DBG_IRQ_OFFSET 0x0C
117 #define C_DBG_DMA_P1_NDFLASH_OFFSET 0x0E
118 #define C_DBG_DMA_P2_OFFSET 0x10
119 #define C_DBG_DMA_P0_OFFSET 0x12
120 #define C_DBG_CLK1_OFFSET 0x14
121 #define C_DBG_PATCH_ND_FLSH_OFFSET 0x16
122 #define C_DBG_IMIF_OFFSET 0x18
123 #define C_DBG_KB_USIM_SHD_OFFSET 0x1A
124 #define C_DBG_USIM_OFFSET 0x1C
125 #define C_DBG_MISC1_OFFSET 0x1E
126 #define C_DBG_MISC2_OFFSET 0x20
127 #define C_DBG_CLK2_OFFSET 0x22
128
129
130 /*
131 * Registers address definition
132 */
133 #define C_CONF_CORE_REG * (volatile SYS_UWORD16 *) (C_MAP_CORE_CONF_BASE + C_CONF_CORE_OFFSET)
134 #define C_CONF_PULL_PWRDN_REG * (volatile SYS_UWORD16 *) (C_MAP_CORE_CONF_BASE + C_CONF_PULL_PWRDN_OFFSET)
135
136 #define C_DBG_CORE1_REG * (volatile SYS_UWORD16 *) (C_MAP_CORE_CONF_BASE + C_DBG_CORE1_OFFSET)
137 #define C_DBG_CORE2_REG * (volatile SYS_UWORD16 *) (C_MAP_CORE_CONF_BASE + C_DBG_CORE2_OFFSET)
138
139 #define C_DBG_IRQ_REG * (volatile SYS_UWORD16 *) (C_MAP_CORE_CONF_BASE + C_DBG_IRQ_OFFSET)
140 #define C_DBG_DMA_P1_NDFLASH_REG * (volatile SYS_UWORD16 *) (C_MAP_CORE_CONF_BASE + C_DBG_DMA_P1_NDFLASH_OFFSET)
141 #define C_DBG_DMA_P2_REG * (volatile SYS_UWORD16 *) (C_MAP_CORE_CONF_BASE + C_DBG_DMA_P2_OFFSET)
142 #define C_DBG_DMA_P0_REG * (volatile SYS_UWORD16 *) (C_MAP_CORE_CONF_BASE + C_DBG_DMA_P0_OFFSET)
143 #define C_DBG_CLK1_REG * (volatile SYS_UWORD16 *) (C_MAP_CORE_CONF_BASE + C_DBG_CLK1_OFFSET)
144 #define C_DBG_PATCH_ND_FLSH_REG * (volatile SYS_UWORD16 *) (C_MAP_CORE_CONF_BASE + C_DBG_PATCH_ND_FLSH_OFFSET)
145 #define C_DBG_IMIF_REG * (volatile SYS_UWORD16 *) (C_MAP_CORE_CONF_BASE + C_DBG_IMIF_OFFSET)
146 #define C_DBG_KB_USIM_SHD_REG * (volatile SYS_UWORD16 *) (C_MAP_CORE_CONF_BASE + C_DBG_KB_USIM_SHD_OFFSET)
147 #define C_DBG_USIM_REG * (volatile SYS_UWORD16 *) (C_MAP_CORE_CONF_BASE + C_DBG_USIM_OFFSET)
148 #define C_DBG_MISC1_REG * (volatile SYS_UWORD16 *) (C_MAP_CORE_CONF_BASE + C_DBG_MISC1_OFFSET)
149 #define C_DBG_MISC2_REG * (volatile SYS_UWORD16 *) (C_MAP_CORE_CONF_BASE + C_DBG_MISC2_OFFSET)
150 #define C_DBG_CLK2_REG * (volatile SYS_UWORD16 *) (C_MAP_CORE_CONF_BASE + C_DBG_CLK2_OFFSET)
151
152
153 /*
154 * DBG_IRQ register definition
155 */
156 /* nCS2 functional pin */
157 #define C_DBG_IRQ_INT4N 0x0001
158 #define C_DBG_IRQ_TPU_WAIT 0x0002
159
160 /* IO_8 functional pin */
161 #define C_DBG_IRQ_SHD_EZ8 0x0004
162 #define C_DBG_IRQ_INT1N 0x0008
163
164 /* NAND_CE1 functional pin : configured in other register : DBG_USIM */
165 #define C_DBG_IRQ_INT10N 0x0010
166
167 /* IO_15 functional pin : already configured in DBG_CLK2 */
168 #define C_DBG_IRQ_NWAIT 0x0020
169
170 /* FDP functional pin */
171 #define C_DBG_IRQ_IACKN 0x0040
172
173 /* IO_10 functional pin */
174 #define C_DBG_IRQ_NMIIT 0x0080
175
176 /* IO_4 functional pin */
177 #define C_DBG_IRQ_IRQ4 0x0100
178
179 /* nSCS1 functional pin */
180 #define C_DBG_IRQ_IRQ14 0x0200
181
182 /* nCS1 functional pin */
183 #define C_DBG_IRQ_ARM_NIRQ_VIEW0 0x0400
184
185 /* IO_12 functional pin */
186 #define C_DBG_IRQ_NCSS2 0x0800
187 #define C_DBG_IRQ_ARM_NIRQ_VIEW1 0x1000
188
189 /* IO_9 functional pin */
190 #define C_DBG_IRQ_NIRQ 0x2000
191
192 /* IO_5 functional pin */
193 #define C_DBG_IRQ_NFIQ 0x4000
194
195
196 /*
197 * DBG_DMA_P1_NDFLASH register definition
198 */
199 /* KBR(3) functional pin */
200 #define C_DBG_DMA_P1_NDFLASH_DMA_REQ_V1 0x0001
201 #define C_DBG_DMA_P1_NDFLASH_ND_FLASH_STATE_3 0x0002
202
203 /* KBR(5) functional pin */
204 #define C_DBG_DMA_P1_NDFLASH_DMA_REQ_S_1 0x0004
205 #define C_DBG_DMA_P1_NDFLASH_ND_FLASH_STATE_4 0x0008
206
207 /* KBC(4) functional pin */
208 #define C_DBG_DMA_P1_NDFLASH_DMA_REQ_P1_0 0x0010
209 #define C_DBG_DMA_P1_NDFLASH_ND_FLASH_CLK_REQ 0x0020
210
211 /* KBC(5) functional pin */
212 #define C_DBG_DMA_P1_NDFLASH_DMA_REQ_P1_1 0x0040
213 #define C_DBG_DMA_P1_NDFLASH_ND_FLASH_STATE_0 0x0080
214
215 /* KBR(0) functional pin */
216 #define C_DBG_DMA_P1_NDFLASH_DMA_REQ_P1_2 0x0100
217 #define C_DBG_DMA_P1_NDFLASH_ND_FLASH_STATE_1 0x0200
218
219 /* KBR(1) functional pin */
220 #define C_DBG_DMA_P1_NDFLASH_DMA_REQ_P1_3 0x0400
221 #define C_DBG_DMA_P1_NDFLASH_ND_FLASH_STATE_2 0x0800
222
223 /* SDMC_DAT(2) functional pin */
224 #define C_DBG_DMA_P1_NDFLASH_NDMA_REQ_VIEW_0 0x1000
225 #define C_DBG_DMA_P1_NDFLASH_MMC_SPI_CS1 0x2000
226
227 /* NAND_RnB functional pin */
228 #define C_DBG_DMA_P1_NDFLASH_NDMA_REQ_VIEW_1 0x4000
229 #define C_DBG_DMA_P1_NDFLASH_SIM_RnW 0x8000
230
231
232 /*
233 * DBG_DMA_P2 register definition
234 */
235 /* ADD_24 functional pin */
236 #define C_DBG_DMA_P2_DMA_REQ_V2 0x0001
237 #define C_DBG_DMA_P2_GPO_2 0x0002
238
239 /* ADD_25 functional pin */
240 #define C_DBG_DMA_P2_DMA_REQ_S2 0x0004
241 #define C_DBG_DMA_P2_GPO_3 0x0008
242
243 /* TSPACT_10 functional pin */
244 #define C_DBG_DMA_P2_DMA_REQUEST_P2_0 0x0010
245
246 /* TSPACT_9 functional pin */
247 #define C_DBG_DMA_P2_DMA_REQUEST_P2_1 0x0020
248
249 /* TSPACT_8 functional pin */
250 #define C_DBG_DMA_P2_DMA_REQUEST_P2_2 0x0040
251
252 /* SDMC_DAT_1 functional pin */
253 #define C_DBG_DMA_P2_DMA_REQUEST_P2_3 0x0080
254 #define C_DBG_DMA_P2_MMC_SPI_CS0 0x0100
255
256
257 /*
258 * DBG_DMA_P0 register definition
259 */
260 /* KBR_2 functional pin */
261 #define C_DBG_DMA_P0_DMA_REQ_V0 0x0001
262 #define C_DBG_DMA_P0_X_A_5 0x0002
263
264 /* KBR_4 functional pin */
265 #define C_DBG_DMA_P0_DMA_REQ_S0 0x0004
266 #define C_DBG_DMA_P0_X_A_6 0x0008
267
268 /* KBC_0 functional pin */
269 #define C_DBG_DMA_P0_DMA_REQUEST_P0_0 0x0010
270
271 /* KBC_1 functional pin */
272 #define C_DBG_DMA_P0_DMA_REQUEST_P0_1 0x0020
273
274 /* KBC_2 functional pin */
275 #define C_DBG_DMA_P0_DMA_REQUEST_P0_2 0x0040
276
277 /* KBC_3 functional pin */
278 #define C_DBG_DMA_P0_DMA_REQUEST_P0_3 0x0080
279
280
281 /*
282 * DBG_CLK1 register definition
283 */
284 /* IO_11 functional pin */
285 #define C_DBG_CLK1_MCLK 0x0001
286
287 /* SPARE_1 functional pin */
288 #define C_DBG_CLK1_DSP_CLKOUT 0x0002
289 #define C_DBG_CLK1_SHPM 0x0004
290
291 /* APLL_DIV_CLK functional pin */
292 #define C_DBG_CLK1_LCD_FIFO_FULL 0x0008
293 #define C_DBG_CLK1_DPLL_CLKOUT 0x0010
294 #define C_DBG_CLK1_APM 0x0020
295
296 /* LT functional pin */
297 #define C_DBG_CLK1_PWL 0x0040
298 #define C_DBG_CLK1_BRIDGE_CLK 0x0080
299
300 /* BU functional pin */
301 #define C_DBG_CLK1_PWT 0x0100
302 #define C_DBG_CLK1_DMA_CLK_REQ 0x0200
303
304 /* DSR_MODEM_1 functional pin */
305 #define C_DBG_CLK1_LPG 0x0400
306
307
308 /*
309 * DBG_PATCH_ND_FLSH register definition
310 */
311 /* LCD_RnW functional pin */
312 #define C_DBG_PATCH_ND_FLSH_PATCH_DETECT 0x0001
313 #define C_DBG_PATCH_ND_FLSH_XDI_O_0 0x0002
314
315 /* LCD_nCS0 functional pin */
316 #define C_DBG_PATCH_ND_FLSH_PATCH_STATE_0 0x0004
317 #define C_DBG_PATCH_ND_FLSH_XDI_O_1 0x0008
318
319 /* LCD_ESTRB functional pin */
320 #define C_DBG_PATCH_ND_FLSH_PATCH_STATE_1 0x0010
321 #define C_DBG_PATCH_ND_FLSH_XDI_O_2 0x0020
322
323 /* LCD_nCS1 functional pin */
324 #define C_DBG_PATCH_ND_FLSH_PATCH_STATE_2 0x0040
325 #define C_DBG_PATCH_ND_FLSH_XDI_O_3 0x0080
326
327 /* LCD_nRESET functional pin */
328 #define C_DBG_PATCH_ND_FLSH_ND_FLASH_CLK_REQ 0x0100
329 #define C_DBG_PATCH_ND_FLSH_XDI_O_4 0x0200
330
331 /* LCD_D_5 functional pin */
332 #define C_DBG_PATCH_ND_FLSH_ND_FLASH_STATE_0 0x0400
333 #define C_DBG_PATCH_ND_FLSH_C_XDI_O_5 0x0800
334
335 /* LCD_RS functional pin */
336 #define C_DBG_PATCH_ND_FLSH_ND_FLASH_STATE_1 0x1000
337 #define C_DBG_PATCH_ND_FLSH_XDI_O_6 0x2000
338
339 /* LCD_D_0 functional pin */
340 #define C_DBG_PATCH_ND_FLSH_ND_FLASH_STATE_2 0x4000
341 #define C_DBG_PATCH_ND_FLSH_XDI_O_7 0x8000
342
343
344 /*
345 * DBG_IMIF register definition
346 */
347 /* LCD_D_3 functional pin */
348 #define C_DBG_IMIF_GEA_WORKING 0x0001
349 #define C_DBG_IMIF_IMIF_CCS_0 0x0002
350 #define C_DBG_IMIF_X_A_2 0x0004
351
352 /* LCD_D_4 functional pin */
353 #define C_DBG_IMIF_GEA_DL_NUL 0x0008
354 #define C_DBG_IMIF_IMIF_CCS_1 0x0010
355 #define C_DBG_IMIF_X_A_3 0x0020
356
357 /* LCD_D_6 functional pin */
358 #define C_DBG_IMIF_IMIF_CCS_2 0x0040
359 #define C_DBG_IMIF_X_A_4 0x0080
360
361 /* LCD_D_7 functional pin */
362 #define C_DBG_IMIF_IMIF_CCS_3 0x0100
363 #define C_DBG_IMIF_XIO_NREADY_MEM 0x0200
364
365 /* NAND_IO_5 functional pin */
366 #define C_DBG_IMIF_IMIF_CS6_0 0x0400
367 #define C_DBG_IMIF_DMA_REQ_SRC_4 0x0800
368
369 /* NAND_nWP1 functional pin */
370 #define C_DBG_IMIF_IMIF_PM 0x1000
371 #define C_DBG_IMIF_USIM_TX_STATE_1 0x4000
372
373
374 /*
375 * DBG_KB_USIM_SHD register definition
376 */
377 /* NAND_RE functional pin */
378 #define C_DBG_KB_USIM_SHD_KB_STATE_0 0x0001
379 #define C_DBG_KB_USIM_SHD_SHD_EZ4KX16 0x0002
380 #define C_DBG_KB_USIM_SHD_USIM_STATE_0 0x0004
381
382 /* NAND_WE functional pin */
383 #define C_DBG_KB_USIM_SHD_KB_STATE_1 0x0008
384 #define C_DBG_KB_USIM_SHD_USIM_STATE_1 0x0010
385 #define C_DBG_KB_USIM_SHD_BRIDGE_EN 0x0020
386
387 /* NAND_CLE functional pin */
388 #define C_DBG_KB_USIM_SHD_KB_STATE_2 0x0040
389 #define C_DBG_KB_USIM_SHD_DSP_NIRQ_VIEW_0 0x0080
390 #define C_DBG_KB_USIM_SHD_USIM_STATE_2 0x0100
391
392 /* NAND_ALE functional pin */
393 #define C_DBG_KB_USIM_SHD_KB_STATE_3 0x0200
394 #define C_DBG_KB_USIM_SHD_DSP_NIRQ_VIEW_1 0x0400
395 #define C_DBG_KB_USIM_SHD_USIM_STATE_3 0x0800
396
397
398 /*
399 * DBG_USIM register definition
400 */
401 /* NAND_IO_8 functional pin */
402 #define C_DBG_USIM_RHEA_NSTROBE 0x0001
403 #define C_DBG_USIM_USIM_RX_STATE_1 0x0002
404
405 /* NAND_CE1 functional pin : configured in other register : DBG_IRQ */
406 #define C_DBG_USIM_RHEA_NREADY 0x0004
407 #define C_DBG_USIM_USIM_TX_STATE_0 0x0008
408
409 /* NAND_ALE functional pin */
410 #define C_DBG_USIM_SHD_EZ9 0x0010
411 #define C_DBG_USIM_SHPM 0x0020
412 #define C_DBG_USIM_USIM_RX_STATE_0 0x0040
413
414 /* NAND_ALE functional pin */
415 #define C_DBG_USIM_SHD_EZ8 0x0080
416 #define C_DBG_USIM_APM 0x0100
417 #define C_DBG_USIM_USIM_START_BIT 0x0200
418
419 /* NAND_ALE functional pin */
420 #define C_DBG_USIM_ND_FLASH_STATE_3 0x0400
421 #define C_DBG_USIM_X_A_0 0x0800
422
423 /* NAND_ALE functional pin */
424 #define C_DBG_USIM_ND_FLASH_STATE_4 0x1000
425 #define C_DBG_USIM_X_A_1 0x2000
426
427
428 /*
429 * DBG_MISC1 register definition
430 */
431 /* nCS3 functional pin */
432 #define C_DBG_MISC1_TOUT1 0x0001
433 #define C_DBG_MISC1_TPU_IDLE 0x0002
434
435 /* MMC_CLK functional pin */
436 #define C_DBG_MISC1_MS_CLK 0x0004
437 #define C_DBG_MISC1_MMC_SPI_CLK 0x0008
438
439 /* IO_13 functional pin */
440 #define C_DBG_MISC1_MCUEN_2 0x0010
441 #define C_DBG_MISC1_MMC_SPI_FREADY 0x0020
442 #define C_DBG_MISC1_ARBITRER_NWAIT 0x0040
443
444 /* SDMC_DAT_0 functional pin */
445 #define C_DBG_MISC1_MS_SDIO 0x0080
446 #define C_DBG_MISC1_MAS_1 0x0100
447
448 /* SDMC_DAT_3 functional pin */
449 #define C_DBG_MISC1_TOUT2 0x0200
450 #define C_DBG_MISC1_MMC_SPI_CS2 0x0400
451 #define C_DBG_MISC1_MAS_0 0x0800
452
453 /* IO_6 functional pin */
454 #define C_DBG_MISC1_XF 0x1000
455
456 /* IO_14 functional pin : already configured in DBG_CLK2 */
457 #define C_DBG_MISC1_NMREQ 0x2000
458 #define C_DBG_MISC1_SHD_EZ9 0x4000
459
460 /* MMC_CMD functional pin */
461 #define C_DBG_MISC1_MS_BS 0x8000
462
463
464 /*
465 * DBG_MISC2 register definition
466 */
467 /* SD_IRDA functional pin */
468 #define C_DBG_MISC2_LCD_FIFO_EMPTY 0x0001
469
470 /* ADD_23 functional pin */
471 #define C_DBG_MISC2_GPO_1 0x0002
472
473 /* EXT_IRQ_1 functional pin */
474 #define C_DBG_MISC2_START_BIT 0x0004
475
476 /* EXT_IRQ_2 functional pin */
477 #define C_DBG_MISC2_X_IOSTRBN 0x0008
478
479 /* NAND_IO_1 functional pin */
480 #define C_DBG_MISC2_NOPC 0x0010
481 #define C_DBG_MISC2_DMA_REQ_SRC_0 0x0020
482 #define C_DBG_MISC2_PATCH_DETECT 0x0040
483
484 /* NAND_IO_2 functional pin */
485 #define C_DBG_MISC2_DMA_REQ_SRC_1 0x0080
486 #define C_DBG_MISC2_PATCH_STATE_0 0x0100
487 #define C_DBG_MISC2_MAS_1 0x0200
488
489 /* NAND_IO_3 functional pin */
490 #define C_DBG_MISC2_MAS_0 0x0400
491 #define C_DBG_MISC2_DMA_REQ_SRC_2 0x0800
492 #define C_DBG_MISC2_PATCH_STATE_1 0x1000
493
494 /* NAND_IO_4 functional pin */
495 #define C_DBG_MISC2_DMA_REQ_SRC_3 0x2000
496 #define C_DBG_MISC2_PATCH_STATE_2 0x4000
497
498 /* ADD_22 functional pin */
499 #define C_DBG_MISC2_GPO_0 0x8000
500
501
502 /*
503 * DBG_CLK2 register definition
504 */
505 /* MCUEN_1 functional pin */
506 #define C_DBG_CLK2_CPORT_CLKIN 0x0001
507
508 /* TSPACT_11 functional pin */
509 #define C_DBG_CLK2_BCLKX 0x0002
510 #define C_DBG_CLK2_DMA_CLK_REQ2 0x0004
511 #define C_DBG_CLK2_CLKM_CLK 0x0008
512
513 /* RX_IRDA functional pin */
514 #define C_DBG_CLK2_CLK16X_IRDA 0x0010
515
516 /* IO_7 functional pin */
517 #define C_DBG_CLK2_CLKX_SPI 0x0020
518
519 /* IO_14 functional pin : already configured in DBG_MISC1 */
520 #define C_DBG_CLK2_PP_CLK_IN 0x0040
521
522 /* IO_15 functional pin : already configured in DBG_IRQ */
523 #define C_DBG_CLK2_PP_CLK_EN 0x0080
524
525
526 /*
527 * DBG_CONF1 register definition
528 */
529 #define C_DBG_CONF1_ARM_IRQ_SEL0_POS 0
530 #define C_DBG_CONF1_ARM_IRQ_SEL1_POS 5
531 #define C_DBG_CONF1_DSP_IRQ_SEL0_POS 10
532
533
534 /*
535 * DBG_CONF2 register definition
536 */
537 #define C_DBG_CONF2_DSP_IRQ_SEL1_POS 0
538 #define C_DBG_CONF2_DMA_REQ_SEL0_POS 5
539 #define C_DBG_CONF2_DMA_REQ_SEL1_POS 10
540
541
542 #define C_DBG_CONF_ARM_IRQ_MASK 0x001F
543 #define C_DBG_CONF_DSP_IRQ_MASK 0x000F
544 #define C_DBG_CONF_DMA_REQ_MASK 0x001F
545
546
547 /*
548 * CONF_CORE register definition
549 */
550 #define C_CONF_CORE_RIF_CLK_POL_POS 5
551 #define C_CONF_CORE_SPI_CLK_POL_POS 6
552
553 #define C_CONF_CORE_RIF_CLK_POL_MASK 0x0001
554 #define C_CONF_CORE_SPI_CLK_POL_MASK 0x0001
555
556
557
558 /****************************************************************************
559 * MACRO DEFINITION
560 ***************************************************************************/
561
562 #define F_DBG_IRQ_CONFIG(d_config) C_DBG_IRQ_REG = d_config
563 #define F_DBG_DMA_P1_NDFLASH_CONFIG(d_config) C_DBG_DMA_P1_NDFLASH_REG = d_config
564 #define F_DBG_DMA_P2_CONFIG(d_config) C_DBG_DMA_P2_REG = d_config
565 #define F_DBG_DMA_P0_CONFIG(d_config) C_DBG_DMA_P0_REG = d_config
566 #define F_DBG_CLK1_CONFIG(d_config) C_DBG_CLK1_REG = d_config
567 #define F_DBG_PATCH_ND_FLSH_CONFIG(d_config) C_DBG_PATCH_ND_FLSH_REG = d_config
568 #define F_DBG_IMIF_CONFIG(d_config) C_DBG_IMIF_REG = d_config
569 #define F_DBG_KB_USIM_SHD_CONFIG(d_config) C_DBG_KB_USIM_SHD_REG = d_config
570 #define F_DBG_USIM_CONFIG(d_config) C_DBG_USIM_REG = d_config
571 #define F_DBG_MISC1_CONFIG(d_config) C_DBG_MISC1_REG = d_config
572 #define F_DBG_MISC2_CONFIG(d_config) C_DBG_MISC2_REG = d_config
573 #define F_DBG_CLK2_CONFIG(d_config) C_DBG_CLK2_REG = d_config
574
575
576 /**************************************************************************
577 *
578 * FUNCTION NAME: F_DBG_CONFIG_VIEW
579 * Configure the ARM_nIRQ_VIEW(1:0), DSP_nIRQ_VIEW(1:0) and
580 * nDMA_REQ_VIEW(1:0).
581 *
582 *
583 * ARGUMENT LIST:
584 *
585 * Argument Description
586 * -------------- --------------------------------------------------------
587 * d_arm_irq_sel0 ARM interrupt index mapped on ARM_nIRQ_VIEW(0) (use index
588 * defined in the Interrupt Handler module).
589 * d_arm_irq_sel1 ARM interrupt index mapped on ARM_nIRQ_VIEW(1) (use index
590 * defined in the Interrupt Handler module).
591 * d_dsp_irq_sel0 DSP interrupt index mapped on DSP_nIRQ_VIEW(0).
592 * d_dsp_irq_sel1 DSP interrupt index mapped on DSP_nIRQ_VIEW(1).
593 * d_dma_req_sel0 DMA request index mapped on nDMA_REQ_VIEW(0) (use index
594 * defined in the DMA module).
595 * d_dma_req_sel1 DMA request index mapped on nDMA_REQ_VIEW(0) (use index
596 * defined in the DMA module).
597 *
598 * RETURN VALUE: None
599 *
600 **************************************************************************/
601
602 #define F_DBG_VIEW_CONFIG(d_arm_irq_sel0, d_arm_irq_sel1, \
603 d_dsp_irq_sel0, d_dsp_irq_sel1, \
604 d_dma_req_sel0, d_dma_req_sel1) { \
605 C_DBG_CORE1_REG = ((d_arm_irq_sel0 & C_DBG_CONF_ARM_IRQ_MASK) << C_DBG_CONF1_ARM_IRQ_SEL0_POS) | \
606 ((d_arm_irq_sel1 & C_DBG_CONF_ARM_IRQ_MASK) << C_DBG_CONF1_ARM_IRQ_SEL1_POS) | \
607 ((d_dsp_irq_sel0 & C_DBG_CONF_DSP_IRQ_MASK) << C_DBG_CONF1_DSP_IRQ_SEL0_POS); \
608 C_DBG_CORE2_REG = ((d_dsp_irq_sel1 & C_DBG_CONF_DSP_IRQ_MASK) << C_DBG_CONF2_DSP_IRQ_SEL1_POS) | \
609 ((d_dma_req_sel0 & C_DBG_CONF_DMA_REQ_MASK) << C_DBG_CONF2_DMA_REQ_SEL0_POS) | \
610 ((d_dma_req_sel1 & C_DBG_CONF_DMA_REQ_MASK) << C_DBG_CONF2_DMA_REQ_SEL1_POS); \
611 }
612
613
614
615 #define F_CONF_RIF_RX_FALLING_EDGE C_CONF_CORE_REG &= ~(C_CONF_CORE_RIF_CLK_POL_MASK << C_CONF_CORE_RIF_CLK_POL_POS)
616 #define F_CONF_RIF_RX_RISING_EDGE C_CONF_CORE_REG |= (C_CONF_CORE_RIF_CLK_POL_MASK << C_CONF_CORE_RIF_CLK_POL_POS)
617
618 #define F_CONF_SPI_RX_FALLING_EDGE C_CONF_CORE_REG &= ~(C_CONF_CORE_SPI_CLK_POL_MASK << C_CONF_CORE_SPI_CLK_POL_POS)
619 #define F_CONF_SPI_RX_RISING_EDGE C_CONF_CORE_REG |= (C_CONF_CORE_SPI_CLK_POL_MASK << C_CONF_CORE_SPI_CLK_POL_POS)
620
621
622
623 /****************************************************************************
624 * STRUCTURE DEFINITION
625 ***************************************************************************/
626
627 /****************************************************************************
628 * PROTOTYPE DEFINITION
629 ***************************************************************************/
630
631
632 #endif /* (CHIPSET == 12) */
633
634
635 #endif /* __SYS_CONF_H__ */