TR16-S is the 16-channel transcoder card, providing 16 TRAU channels.
Examination of the board reveals the following major components:

Global for the whole TR16-S:

One Lattice ispLSI1032E: a programmable logic device, non-volatile configuration
bits inside.

One CY62128BLL-70SI chip: 128K x 8 static RAM.

Replicated 16x, one set for each TRAU channel:

One DSP chip, has these markings in addition to TI logo:

	TRLPRB 1.1
	D36884PZ-66
	ADW-4BAORLW

I had no success in finding any documentation for this DSP chip - was it one of
those semi-custom Skunkworks parts without public documentation?  I surmise
(without any proof!) that it is probably based on C54x architecture.

In addition to this DSP, there is one more chip replicated 16x per channel, one
next to each DSP: IDT 71V016, 64K x 16 static RAM.

Note the absence of any flash or other non-volatile memory chips: there is
non-volatile storage of configuration bits inside the Lattic PLD, but that's
just logic, no code.  The available documentation for TCSM2 strongly suggests
that operational DSP code is loaded from TRCO, presumably on each system boot,
but what about boot code, how does the "cold" TR16-S card communicate with TRCO?
The custom DSP ASICs probably have some ROM in them, supporting boot and maybe
providing some common routines or tables for the operational code, who knows...