FreeCalypso > hg > gsm-net-reveng
comparison tcsm2-notes/tr16 @ 16:2daf8f209707
tcsm2-notes: initial observations on boards
| author | Mychaela Falconia <falcon@freecalypso.org> |
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| date | Wed, 29 May 2024 02:26:13 +0000 |
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| 15:86a10ba0a1f8 | 16:2daf8f209707 |
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| 1 TR16-S is the 16-channel transcoder card, providing 16 TRAU channels. | |
| 2 Examination of the board reveals the following major components: | |
| 3 | |
| 4 Global for the whole TR16-S: | |
| 5 | |
| 6 One Lattice ispLSI1032E: a programmable logic device, non-volatile configuration | |
| 7 bits inside. | |
| 8 | |
| 9 One CY62128BLL-70SI chip: 128K x 8 static RAM. | |
| 10 | |
| 11 Replicated 16x, one set for each TRAU channel: | |
| 12 | |
| 13 One DSP chip, has these markings in addition to TI logo: | |
| 14 | |
| 15 TRLPRB 1.1 | |
| 16 D36884PZ-66 | |
| 17 ADW-4BAORLW | |
| 18 | |
| 19 I had no success in finding any documentation for this DSP chip - was it one of | |
| 20 those semi-custom Skunkworks parts without public documentation? I surmise | |
| 21 (without any proof!) that it is probably based on C54x architecture. | |
| 22 | |
| 23 In addition to this DSP, there is one more chip replicated 16x per channel, one | |
| 24 next to each DSP: IDT 71V016, 64K x 16 static RAM. | |
| 25 | |
| 26 Note the absence of any flash or other non-volatile memory chips: there is | |
| 27 non-volatile storage of configuration bits inside the Lattic PLD, but that's | |
| 28 just logic, no code. The available documentation for TCSM2 strongly suggests | |
| 29 that operational DSP code is loaded from TRCO, presumably on each system boot, | |
| 30 but what about boot code, how does the "cold" TR16-S card communicate with TRCO? | |
| 31 The custom DSP ASICs probably have some ROM in them, supporting boot and maybe | |
| 32 providing some common routines or tables for the operational code, who knows... |