# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1521357746 0
# Node ID da6df2c626cf2b1dd9f50e6a542a9a394b48d1d9
# Parent  be2683e1ac5eabb039669bdbe6cbdefb3d3d9dbb
target-utils: wait for FIFO not full in serial_out() instead of FIFO empty

diff -r be2683e1ac5e -r da6df2c626cf target-utils/libbase/serio.S
--- a/target-utils/libbase/serio.S	Fri Mar 16 01:59:34 2018 +0000
+++ b/target-utils/libbase/serio.S	Sun Mar 18 07:22:26 2018 +0000
@@ -10,9 +10,9 @@
 serial_out:
 	ldr	r1, =uart_base
 	ldr	r2, [r1]
-1:	ldrb	r3, [r2, #NS16550_LSR]
-	tst	r3, #NS16550_LSR_THRE
-	beq	1b
+1:	ldrb	r3, [r2, #0x11]		@ Calypso UART non-std register SSR
+	tst	r3, #0x01		@ Tx FIFO full flag
+	bne	1b
 	strb	r0, [r2, #NS16550_THR]
 	bx	lr