# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1549732557 0
# Node ID d96ea6ae6aa52ca968cfa6a56df2a673b40bd6ec
# Parent  3884d823b36e1ab4b5770aebe15d8dbeaf533de7
simtest: setup implemented

diff -r 3884d823b36e -r d96ea6ae6aa5 target-utils/simtest/Makefile
--- a/target-utils/simtest/Makefile	Sat Feb 09 08:09:32 2019 +0000
+++ b/target-utils/simtest/Makefile	Sat Feb 09 17:15:57 2019 +0000
@@ -5,7 +5,7 @@
 OBJCOPY=arm-elf-objcopy
 
 PROG=	simtest
-OBJS=	crt0.o cmdtab.o main.o poll.o volt.o
+OBJS=	crt0.o cmdtab.o main.o poll.o setup.o volt.o
 LIBS=	../libcommon/libcommon.a ../libprintf/libprintf.a ../libbase/libbase.a \
 	../libc/libc.a
 LIBGCC=	`${CC} -print-file-name=libgcc.a`
diff -r 3884d823b36e -r d96ea6ae6aa5 target-utils/simtest/cmdtab.c
--- a/target-utils/simtest/cmdtab.c	Sat Feb 09 08:09:32 2019 +0000
+++ b/target-utils/simtest/cmdtab.c	Sat Feb 09 17:15:57 2019 +0000
@@ -7,6 +7,7 @@
 extern void cmd_r8();
 extern void cmd_r16();
 extern void cmd_r32();
+extern void cmd_setup();
 extern void cmd_volt();
 extern void cmd_w8();
 extern void cmd_w16();
@@ -28,6 +29,7 @@
 	{"r8", cmd_r8},
 	{"r16", cmd_r16},
 	{"r32", cmd_r32},
+	{"setup", cmd_setup},
 	{"volt", cmd_volt},
 	{"w8", cmd_w8},
 	{"w16", cmd_w16},
diff -r 3884d823b36e -r d96ea6ae6aa5 target-utils/simtest/poll.c
--- a/target-utils/simtest/poll.c	Sat Feb 09 08:09:32 2019 +0000
+++ b/target-utils/simtest/poll.c	Sat Feb 09 17:15:57 2019 +0000
@@ -12,7 +12,7 @@
 {
 	u32 drx;
 
-	if (SIMREGS.stat & 3)
+	if (SIMREGS.stat & SIM_STAT_FEMPTY)
 		return;
 	drx = SIMREGS.drx & 0xFF;
 	printf("%02X ", drx);
diff -r 3884d823b36e -r d96ea6ae6aa5 target-utils/simtest/setup.c
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/target-utils/simtest/setup.c	Sat Feb 09 17:15:57 2019 +0000
@@ -0,0 +1,56 @@
+#include "types.h"
+#include "abbdefs.h"
+#include "simregs.h"
+
+#define	WAIT_ONE_TDMA	48000
+
+extern u16 abb_reg_read();
+extern void abb_reg_write();
+
+u16 conf1_reg;
+
+void
+cmd_setup(argbulk)
+	char *argbulk;
+{
+	u16 abb_sim_reg;
+
+	abb_sim_reg = abb_reg_read(VRPCSIM);
+	if (!(abb_sim_reg & 2)) {
+		printf("ERROR: VRSIM is not enabled\n");
+		return;
+	}
+	if (!(abb_sim_reg & 4)) {
+		printf("ERROR: VRSIM is not in proper regulation\n");
+		return;
+	}
+
+	/* TI's SIM_ManualStart() code follows */
+	SIMREGS.conf1 = conf1_reg = 0x8004;
+	SIMREGS.cmd = SIM_CMD_CLKEN;
+
+	SIMREGS.cmd = SIM_CMD_CLKEN | SIM_CMD_STOP;
+	wait_ARM_cycles(WAIT_ONE_TDMA * 4);
+
+	SIMREGS.cmd = SIM_CMD_CLKEN | SIM_CMD_SWRST;
+	wait_ARM_cycles(WAIT_ONE_TDMA);
+
+	SIMREGS.conf2  = 0x0940;
+
+	//enter in manual mode to start the ATR sequence
+	SIMREGS.conf1 = conf1_reg |= SIM_CONF1_BYPASS;
+	wait_ARM_cycles(WAIT_ONE_TDMA);
+
+	SIMREGS.conf1 = conf1_reg |= SIM_CONF1_SVCCLEV;
+	wait_ARM_cycles(WAIT_ONE_TDMA);
+
+	abb_sim_reg |= 8;
+	abb_reg_write(VRPCSIM, abb_sim_reg);
+	wait_ARM_cycles(WAIT_ONE_TDMA);
+
+	SIMREGS.conf1 = conf1_reg &= ~SIM_CONF1_SIOLOW;
+	wait_ARM_cycles(WAIT_ONE_TDMA);
+
+	SIMREGS.conf1 = conf1_reg |= SIM_CONF1_SCLKEN;
+	SIMREGS.conf1 = conf1_reg &= ~SIM_CONF1_TXRX; //set to receive mode
+}
diff -r 3884d823b36e -r d96ea6ae6aa5 target-utils/simtest/simregs.h
--- a/target-utils/simtest/simregs.h	Sat Feb 09 08:09:32 2019 +0000
+++ b/target-utils/simtest/simregs.h	Sat Feb 09 17:15:57 2019 +0000
@@ -15,3 +15,53 @@
 };
 
 #define	SIMREGS	(*(volatile struct sim_registers *) SIM_BASE_ADDR)
+
+/*
+ * Bit definitions 
+ */ 
+// control regidter
+#define SIM_CMD_CRST          0x0001
+#define SIM_CMD_SWRST         0x0002
+#define SIM_CMD_STOP          0x0004
+#define SIM_CMD_START         0x0008
+#define SIM_CMD_CLKEN         0x0010	
+
+// status register
+#define SIM_STAT_CD           0x0001   // card present
+#define SIM_STAT_TXPAR        0x0002   // transmit parity status
+#define SIM_STAT_FFULL        0x0004   // fifo full
+#define SIM_STAT_FEMPTY       0x0008   // fifo empty
+
+// configuration register
+#define SIM_CONF1_CHKPAR      0x0001   // enable receipt check parity
+#define SIM_CONF1_CONV        0x0002   // coding convention
+#define SIM_CONF1_TXRX        0x0004   // SIO line direction
+#define SIM_CONF1_SCLKEN      0x0008   // enable SIM clock
+#define SIM_CONF1_RSVD        0x0010   // reserved
+#define SIM_CONF1_SCLKDIV	  0x0020   // SIM clock frquency
+#define SIM_CONF1_SCLKLEV	  0x0040   // SIM clock idle level
+#define SIM_CONF1_ETU	      0x0080   // ETU period
+#define SIM_CONF1_BYPASS      0x0100   // bypass hardware timers
+#define SIM_CONF1_SVCCLEV     0x0200
+#define SIM_CONF1_SRSTLEV     0x0400
+#define SIM_CONF1_SIOLOW      0x8000   //force SIO to low level	 
+
+// interrupt status register
+#define SIM_IT_NATR           0x0001   // No answer to reset
+#define SIM_IT_WT             0x0002
+#define SIM_IT_ITOV           0x0004   
+#define SIM_IT_ITTX           0x0008   // Transmit
+#define SIM_IT_ITRX           0x0010   // Receipt
+
+#define SIM_IT_CD             0x0001   // Card insertion/extraction
+
+// interrupt mask register
+#define SIM_MASK_NATR         0x0001   // No answer to reset
+#define SIM_MASK_WT           0x0002
+#define SIM_MASK_OV           0x0004
+#define SIM_MASK_TX           0x0008   // Transmit
+#define SIM_MASK_RX           0x0010   // Receipt
+#define SIM_MASK_CD           0x0020   // Card insertion/extraction	
+
+// receveid byte register
+#define SIM_DRX_STATRXPAR     0x0100   // received byte parity status