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comparison target-utils/libbase/abbdrv.c @ 496:3d73d4d3527f

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target-utils: removed osmo_delay_ms() from ABB access code
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 25 May 2019 20:17:27 +0000
parents e7502631a0f9
children 74610c4f10f7
comparison
equal deleted inserted replaced
495:06ad5e30e8d0 496:3d73d4d3527f
56 56
57 tx = (REG_ADDR(reg) << 1) | 1; 57 tx = (REG_ADDR(reg) << 1) | 1;
58 58
59 /* A read cycle contains two SPI transfers */ 59 /* A read cycle contains two SPI transfers */
60 spi_xfer(TWL3025_DEV_IDX, 16, &tx, &rx); 60 spi_xfer(TWL3025_DEV_IDX, 16, &tx, &rx);
61 osmo_delay_ms(1); 61 /* delay of seven 13MHz cycles */
62 wait_ARM_cycles(7);
62 spi_xfer(TWL3025_DEV_IDX, 16, &tx, &rx); 63 spi_xfer(TWL3025_DEV_IDX, 16, &tx, &rx);
63 64
64 rx >>= 6; 65 rx >>= 6;
65 66
66 return rx; 67 return rx;
83 return(0); 84 return(0);
84 spi_init(); 85 spi_init();
85 abb_select_page(0); 86 abb_select_page(0);
86 /* CLK13M enable */ 87 /* CLK13M enable */
87 abb_reg_write(TOGBR2, TOGBR2_ACTS); 88 abb_reg_write(TOGBR2, TOGBR2_ACTS);
88 osmo_delay_ms(1); 89 /* ABB_Wait_IBIC_Access() delay of 210 us */
90 wait_ARM_cycles(210 * 13);
89 /* for whatever reason we need to do this twice */ 91 /* for whatever reason we need to do this twice */
90 abb_reg_write(TOGBR2, TOGBR2_ACTS); 92 abb_reg_write(TOGBR2, TOGBR2_ACTS);
91 osmo_delay_ms(1); 93 /* ABB_Wait_IBIC_Access() delay of 210 us */
94 wait_ARM_cycles(210 * 13);
92 abb_state_initdone = 1; 95 abb_state_initdone = 1;
93 return(1); 96 return(1);
94 } 97 }
95 98
96 void 99 void