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doc/How-flash-really-works: article written
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 09 Dec 2023 09:08:19 +0000
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1 How NOR flash memory really works
2 =================================
3
4 The type of flash memory used in Calypso GSM devices is formally known as NOR
5 flash. Most embedded software programmers and tinkerers know the fundamental
6 principle of how NOR flash works: any bit can be transitioned from a '1' to a
7 '0' at any time in any combination (an operation called programming), but the
8 opposite transition (from '0' to '1' bits, an operation called erasure) can only
9 be done on fairly large sectors - you can erase a sector and make it all 1s,
10 but changing bits from 0 to 1 individually or in any smaller granularity
11 (smaller than a sector) is impossible.
12
13 What many "software-minded" programmers and tinkerers don't realize, however,
14 is that sector erasure is not an elementary or atomic operation that magically
15 "makes all bits 1s" in one motion. Instead it is a complex process with two or
16 three substeps:
17
18 1) Before starting the physical process of erasure, one has to go through all
19 bits in the to-be-erased sector and make them all 0s. Any bits that are in
20 '1' state when the sector erase operation is commanded MUST be programmed to
21 '0' state before the actual erasure begins! In the language of flash chip
22 industry, this step is called preprogramming. In the case of flash chips
23 that are used in Calypso GSM devices (all known ones), this preprogramming
24 step is done internally by the chip, so that you as the user or software
25 developer are not aware of it - but it is there nonetheless. The chip does
26 NOT magically "wave" all bits in the sector into '1' state, instead it first
27 makes them all '0' internally, and only then erases.
28
29 2) Once every bit in the sector is in '0' state, the real physics of erasure
30 begins. All bit cells in the sector are physically acted upon at once in
31 this step, and because it is a probabilistic process involving a Gaussian
32 distribution, all bit cells need to be in the fully programmed state before
33 they begin their shared journey toward the erased state.
34
35 3) The step of preprogramming every bit to 0 prior to erasure prevents the
36 absolutely unacceptable condition of gross overerasure - but given the
37 Gaussian distribution, some bit cells may still get a little overerased.
38 Many (most? all? not sure) flash chips therefore implement a third internal
39 step before the software-visible "erase" operation is declared complete:
40 they go through all bit cells in the just-erased sector, check for
41 overerasure, and "soft-program" (move slightly to the right in the Vt
42 distribution) any overerased cells. This step is called post-erase
43 conditioning or recovery.
44
45 The above process was originally explained to me (Mother Mychaela) some years
46 ago (around 2008, IIRC) by a Spansion support engineer on a conference call at
47 my then day job - it was a project for a customer who was big and powerful
48 enough to get top-tier support from chip vendors. More recently, however, some
49 other flash vendors have posted public documents that provide the same
50 explanation - here is one from Renesas/Adesto:
51
52 https://www.freecalypso.org/pub/embedded/flash/REN_an500_APN_20210702_1.pdf
53
54 Even though the above document was written by Renesas (or more precisely, the
55 part that was originally Adesto), the theory described therein applies just as
56 well to Intel, Spansion and Samsung flash chips that are used in Calypso GSM
57 devices. For anyone who wishes to know how NOR flash memory really works, I
58 strongly recommend reading that Renesas appnote - it is a good description.
59
60 Additional note on terminology: describing the two states of a flash memory cell
61 as '0' and '1', like I did above, is only a convenience for software-minded
62 people. A more proper view is to think in terms of a "programmed state" and an
63 "erased state" for each bit cell. History and tradition are such that flash
64 chips return '0' on read in the programmed state and '1' in the erased state
65 (this tradition probably originates from the fact that the actual NV storage
66 element, a transistor, conducts read current in the erased state), at least for
67 the main flash array - however, when flash memory elements are used for
68 additional purposes such as write protection controls, it is best to think
69 natively in terms of programmed and erased states. For the latter kind of
70 special applications, an opposite polarity may be applied in read-bit values.
71
72 One straightforward take-away from this theory is that flash endurance is really
73 about program-erase cycles, rather than number of program or number of erase
74 operations. Every time you give a sector erase command, every bit in that
75 sector cycles through the fully programmed (0) state first before becoming
76 erased (1), irrespective of whether or not you programmed into it on your own!
77 Hence every bit-cell of the affected sector always goes through a full
78 program-erase cycle, and all bits in a given sector are always cycled equally,
79 irrespective of whether they get written with mostly-0s or mostly-1s in between
80 erase cycles.
81
82 Another situation where this raw physics gets exposed to the user is the case
83 of special-purpose non-volatile bits in flash chips outside of the main flash
84 memory array - for example, Persistent Protection Bits (PPBs) in some Spansion
85 and Samsung flash chips. While program and erase commands for the main flash
86 array invoke chip-internal mechanisms that take care of everything and present
87 a sane model of 0s and 1s to software, Spansion PL-J PPB program and erase
88 commands expose raw guts: there is a command that applies a raw program pulse
89 to a single PPB, and there is a command that applies a raw erase pulse to the
90 NV memory element (like a little sector of its own) that holds all PPBs.
91 Applying the erase pulse without preprogramming every PPB first would be very
92 bad (see Renesas appnote about the badness of overerasure) - hence in a seeming
93 paradox, one has to explicitly lock every sector before applying PPB erase
94 pulses that will eventually unlock everything!
95
96 Our flash ppb-erase-all command does implement the preprogramming step before
97 actual erasure, and the present document (hopefully) explains why.