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comparison target-utils/calversion/dsp_bringup.c @ 441:1dcc9e4b71fd

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target-utils/calversion: program written, compiles
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 26 Dec 2018 06:40:02 +0000
parents
children ca98f800bbf3
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440:44f73d56b6f5 441:1dcc9e4b71fd
1 /*
2 * This module contains the dsp_power_on() function from TCS211,
3 * stripped and adapted for the present DSP version determination
4 * standalone program.
5 */
6
7 #include "types.h"
8 #include "leadapi.h"
9 #include "dsp_const.h"
10 #include "dsp_defty.h"
11
12 /* definitions originally in l1_types.h */
13
14 typedef unsigned char BOOL;
15 typedef char CHAR;
16
17 typedef unsigned char UWORD8;
18 typedef signed char WORD8;
19
20 typedef unsigned short UWORD16;
21 typedef short WORD16;
22
23 typedef unsigned long UWORD32;
24 typedef long WORD32;
25
26 /* definitions originally in l1_confg.h */
27
28 #define DSP_START 0x7000
29 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
30
31 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
32
33 #define C_DSP_SW_WORK_AROUND 0x000E
34
35 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
36 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
37 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
38
39 /* DSP reset control register definitions */
40
41 #define MEM_CLKM_ADDR 0xfffffd00 /* CLKM registers addr. */
42 #define CLKM_CNTL_RST (MEM_CLKM_ADDR + 4) /* CLKM Reset Control reg. */
43
44 #define CLKM_LEAD_RST 0x0002
45 #define CLKM_EXT_RST 0x0004
46
47 /*-------------------------------------------------------*/
48 /* dsp_power_on() */
49 /*-------------------------------------------------------*/
50 /* Parameters : */
51 /* Return : */
52 /* Functionality : */
53 /* Remarq : USART Buffer is 256 characters. While USART*/
54 /* is not run during Application_Initialize */
55 /* (hisrs not served because Nucleus scheduler*/
56 /* is not running yet) : */
57 /* ==> check string size < 256 !!!!!! */
58 /*-------------------------------------------------------*/
59 void dsp_power_on(void)
60 {
61 UWORD16 dsp_start_address;
62 UWORD16 param_size;
63
64 API i;
65 volatile API *pt;
66 WORD16 j;
67
68 volatile T_NDB_MCU_DSP * dsp_ndb_ptr;
69
70 static API_SIGNED param_tab[] = {
71
72 D_TRANSFER_RATE,
73
74 // ..................Latencies
75 D_LAT_MCU_BRIDGE, D_LAT_MCU_HOM2SAM,
76
77 D_LAT_MCU_BEF_FAST_ACCESS, D_LAT_DSP_AFTER_SAM,
78
79 //...................p_gprs_install_adress
80 D_HOLE,
81
82 //...................d_misc_config
83 D_MISC_CONFIG,
84
85 //...................d_cn_sw_workaround
86 C_DSP_SW_WORK_AROUND,
87
88 //...................Reserved
89 D_HOLE, D_HOLE,
90 D_HOLE, D_HOLE,
91
92 //...................Frequency burst
93 D_FB_MARGIN_BEG, D_FB_MARGIN_END,
94 D_NSUBB_IDLE, D_NSUBB_DEDIC, D_FB_THR_DET_IACQ,
95 D_FB_THR_DET_TRACK,
96 //...................Demodulation
97 D_DC_OFF_THRES, D_DUMMY_THRES, D_DEM_POND_GEWL,
98 D_DEM_POND_RED,
99 //...................TCH Full Speech
100 D_MACCTHRESH1, D_MLDT, D_MACCTHRESH,
101 D_GU, D_GO, D_ATTMAX,
102 D_SM, D_B,
103
104 //...................V42 bis
105 D_V42B_SWITCH_HYST, D_V42B_SWITCH_MIN, D_V42B_SWITCH_MAX,
106 D_V42B_RESET_DELAY,
107
108 //...................TCH Half Speech
109 D_LDT_HR, D_MACCTRESH_HR, D_MACCTRESH1_HR,
110 D_GU_HR, D_GO_HR, D_B_HR,
111 D_SM_HR, D_ATTMAX_HR,
112
113 //...................Added variables for EFR
114 C_MLDT_EFR, C_MACCTHRESH_EFR, C_MACCTHRESH1_EFR,
115 C_GU_EFR, C_GO_EFR, C_B_EFR,
116 C_SM_EFR, C_ATTMAX_EFR,
117
118 //...................Full rate variables
119 D_SD_MIN_THR_TCHFS,
120 D_MA_MIN_THR_TCHFS, D_MD_MAX_THR_TCHFS, D_MD1_MAX_THR_TCHFS,
121
122 //...................TCH Half Speech
123 D_SD_MIN_THR_TCHHS, D_MA_MIN_THR_TCHHS, D_SD_AV_THR_TCHHS,
124 D_MD_MAX_THR_TCHHS, D_MD1_MAX_THR_TCHHS,
125
126 //...................TCH Enhanced Full Rate Speech
127 D_SD_MIN_THR_TCHEFS, D_MA_MIN_THR_TCHEFS, D_MD_MAX_THR_TCHEFS,
128 D_MD1_MAX_THR_TCHEFS, D_WED_FIL_INI,
129
130 D_WED_FIL_TC, D_X_MIN, D_X_MAX,
131 D_SLOPE, D_Y_MIN, D_Y_MAX,
132 D_WED_DIFF_THRESHOLD,D_MABFI_MIN_THR_TCHHS,D_FACCH_THR,
133
134 D_MAX_OVSPD_UL, D_SYNC_THRES, D_IDLE_THRES,
135 D_M1_THRES, D_MAX_OVSP_DL, D_GSM_BGD_MGT
136 };
137 param_size = 79;
138
139 // NDB pointer.
140 dsp_ndb_ptr = (volatile T_NDB_MCU_DSP *) NDB_ADR;
141
142 //-------------
143 // DSP STARTUP
144 //-------------
145 {
146 // Release Lead reset before DSP code/patch download to insure proper reset of DSP
147 printf("Releasing DSP core from reset\n");
148 (*(unsigned short *) CLKM_CNTL_RST) &= ~CLKM_LEAD_RST;
149
150 // GSM 1.5
151 //-----------------------------------------------------------------
152 // After RESET release, DSP is in SAM Mode ! while API_CNTR (0xF900)
153 // register is in reset state: HOM mode, PLL off, Bridge off. No ws
154 // are applied for MCU<-->API access !!!!! So, MCU must wait for
155 // end of Leadboot execution before accessing API.
156 //wait_ARM_cycles(convert_nanosec_to_cycles(10000)); // wait 10us
157 osmo_delay_ms(10);
158
159 // NO DOWNLOAD...
160 {
161 // Wait for READY status from DSP.
162 printf("Waiting for DSP bootloader READY status\n");
163 while(*((volatile UWORD16 *)DOWNLOAD_STATUS) != LEAD_READY);
164
165 // Set DSP start address.
166 dsp_start_address = DSP_START;
167 }
168 }
169
170 //--------------------------------------------------------------
171 // Loading of NDB parameters.......
172 //--------------------------------------------------------------
173 printf("Loading NDB parameters\n");
174 // Initialize background control variable to No background. Background tasks can be launch in GPRS
175 // as in GSM.
176 dsp_ndb_ptr->d_background_enable = 0;
177 dsp_ndb_ptr->d_background_abort = 0;
178 dsp_ndb_ptr->d_background_state = 0;
179 dsp_ndb_ptr->d_debug_ptr = 0x0074;
180 dsp_ndb_ptr->d_debug_bk = 0x0001;
181 dsp_ndb_ptr->d_pll_config = C_PLL_CONFIG;
182 dsp_ndb_ptr->p_debug_buffer = C_DEBUG_BUFFER_ADD;
183 dsp_ndb_ptr->d_debug_buffer_size = C_DEBUG_BUFFER_SIZE;
184 dsp_ndb_ptr->d_debug_trace_type = C_DEBUG_TRACE_TYPE;
185
186 // Deep Sleep work around used on Calypso
187 // This init is used to backward compatibility with old patch.
188 dsp_ndb_ptr->d_dsp_state = C_DSP_IDLE3;
189
190 dsp_ndb_ptr->d_audio_gain_ul = 0;
191 dsp_ndb_ptr->d_audio_gain_dl = 0;
192
193 // for patch >= 2100, use new AEC
194 dsp_ndb_ptr->d_es_level_api = 0x5213;
195 dsp_ndb_ptr->d_mu_api = 0x5000;
196
197 //--------------------------------------------------------------
198 // Loading of PARAM area.......
199 //--------------------------------------------------------------
200 printf("Loading PARAM area\n");
201 // Load PARAM memory...
202 pt = (volatile API *) PARAM_ADR;
203
204 for (i=0; i<param_size; i++) *pt++ = param_tab[i];
205
206 {
207 T_PARAM_MCU_DSP *pt_param = (T_PARAM_MCU_DSP *) PARAM_ADR;
208
209 // "d_gprs_install_address" has to be set only if no PATCH is download, i.e.
210 // "d_gprs_install_address" is automatically set by DSP if a PATCH is download
211 pt_param->d_gprs_install_address = INSTALL_ADD;
212 }
213
214 printf("Booting DSP main code\n");
215 *(volatile UWORD16 *) DOWNLOAD_SIZE = 0; // Size=0 to force DSP to start from address...
216 *(volatile UWORD16 *) DOWNLOAD_ADDR = dsp_start_address; // Start address.
217 *(volatile UWORD16 *) DOWNLOAD_STATUS = BLOCK_READY; // Start DSP...
218
219 osmo_delay_ms(50);
220 printf("DSP reports version 0x%04X 0x%04X\n",
221 dsp_ndb_ptr->d_version_number1, dsp_ndb_ptr->d_version_number2);
222 }