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comparison target-utils/libbase/waitarm.S @ 495:06ad5e30e8d0

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target-utils: wait_ARM_cycles() changed to 4 cycles per loop
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 25 May 2019 18:51:19 +0000
parents 6228d27738d1
children
comparison
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494:547c540448e5 495:06ad5e30e8d0
1 /* 1 /*
2 * This assembly module provides a wait_ARM_cycles() function just like 2 * This assembly module provides a wait_ARM_cycles() function similar to
3 * in TI's firmware; it is meant to gradually replace and phase out 3 * the one in TI's firmware; it is meant to gradually replace and phase out
4 * osmo_delay_ms(). One loop count for this function equals 5 ARM clock 4 * osmo_delay_ms(). One loop count for this function equals 4 ARM clock
5 * cycles when running out of IRAM. 5 * cycles when running out of IRAM; if the ARM clock is 52 MHz, 13 loop counts
6 * equal one microsecond.
7 *
8 * Note the instruction sequence difference from TI's firmware version:
9 * we use the SUBS instruction (equivalent of plain SUB in Thumb) and omit
10 * the CMP, which is why our version is 4 cycles per loop (when running
11 * out of IRAM), as opposed to 5 cycles per loop (plus wait states as they
12 * execute from flash) in TI's fw version.
6 */ 13 */
7 14
8 .text 15 .text
9 .code 32 16 .code 32
10 .globl wait_ARM_cycles 17 .globl wait_ARM_cycles
11 wait_ARM_cycles: 18 wait_ARM_cycles:
12 cmp r0, #0 19 cmp r0, #0
13 bxeq lr 20 bxeq lr
14 1: sub r0, r0, #1 21 1: subs r0, r0, #1
15 cmp r0, #0
16 bne 1b 22 bne 1b
17 bx lr 23 bx lr