FreeCalypso > hg > freecalypso-tools
annotate target-utils/libbase/waitarm.S @ 1014:961efadd530a default tip
fc-shell TCH DL handler: add support for CSD modes
TCH DL capture mechanism in FC Tourmaline firmware has been extended
to support CSD modes in addition to speech - add the necessary support
on the host tools side.
It needs to be noted that this mechanism in its present state does NOT
provide the debug utility value that was sought: as we learned only
after the code was implemented, TI's DSP has a misfeature in that the
buffer we are reading (a_dd_0[]) is zeroed out when the IDS block
is enabled, i.e., we are reading all zeros and not the real DL bits
we were after. But since the code has already been written, we are
keeping it - perhaps we can do some tests with IDS disabled.
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Tue, 26 Nov 2024 06:27:43 +0000 |
parents | 06ad5e30e8d0 |
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rev | line source |
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453
6228d27738d1
target-utils: wait_ARM_cycles() added to libbase
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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1 /* |
495
06ad5e30e8d0
target-utils: wait_ARM_cycles() changed to 4 cycles per loop
Mychaela Falconia <falcon@freecalypso.org>
parents:
453
diff
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2 * This assembly module provides a wait_ARM_cycles() function similar to |
06ad5e30e8d0
target-utils: wait_ARM_cycles() changed to 4 cycles per loop
Mychaela Falconia <falcon@freecalypso.org>
parents:
453
diff
changeset
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3 * the one in TI's firmware; it is meant to gradually replace and phase out |
06ad5e30e8d0
target-utils: wait_ARM_cycles() changed to 4 cycles per loop
Mychaela Falconia <falcon@freecalypso.org>
parents:
453
diff
changeset
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4 * osmo_delay_ms(). One loop count for this function equals 4 ARM clock |
06ad5e30e8d0
target-utils: wait_ARM_cycles() changed to 4 cycles per loop
Mychaela Falconia <falcon@freecalypso.org>
parents:
453
diff
changeset
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5 * cycles when running out of IRAM; if the ARM clock is 52 MHz, 13 loop counts |
06ad5e30e8d0
target-utils: wait_ARM_cycles() changed to 4 cycles per loop
Mychaela Falconia <falcon@freecalypso.org>
parents:
453
diff
changeset
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6 * equal one microsecond. |
06ad5e30e8d0
target-utils: wait_ARM_cycles() changed to 4 cycles per loop
Mychaela Falconia <falcon@freecalypso.org>
parents:
453
diff
changeset
|
7 * |
06ad5e30e8d0
target-utils: wait_ARM_cycles() changed to 4 cycles per loop
Mychaela Falconia <falcon@freecalypso.org>
parents:
453
diff
changeset
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8 * Note the instruction sequence difference from TI's firmware version: |
06ad5e30e8d0
target-utils: wait_ARM_cycles() changed to 4 cycles per loop
Mychaela Falconia <falcon@freecalypso.org>
parents:
453
diff
changeset
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9 * we use the SUBS instruction (equivalent of plain SUB in Thumb) and omit |
06ad5e30e8d0
target-utils: wait_ARM_cycles() changed to 4 cycles per loop
Mychaela Falconia <falcon@freecalypso.org>
parents:
453
diff
changeset
|
10 * the CMP, which is why our version is 4 cycles per loop (when running |
06ad5e30e8d0
target-utils: wait_ARM_cycles() changed to 4 cycles per loop
Mychaela Falconia <falcon@freecalypso.org>
parents:
453
diff
changeset
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11 * out of IRAM), as opposed to 5 cycles per loop (plus wait states as they |
06ad5e30e8d0
target-utils: wait_ARM_cycles() changed to 4 cycles per loop
Mychaela Falconia <falcon@freecalypso.org>
parents:
453
diff
changeset
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12 * execute from flash) in TI's fw version. |
453
6228d27738d1
target-utils: wait_ARM_cycles() added to libbase
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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13 */ |
6228d27738d1
target-utils: wait_ARM_cycles() added to libbase
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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14 |
6228d27738d1
target-utils: wait_ARM_cycles() added to libbase
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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15 .text |
6228d27738d1
target-utils: wait_ARM_cycles() added to libbase
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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16 .code 32 |
6228d27738d1
target-utils: wait_ARM_cycles() added to libbase
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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17 .globl wait_ARM_cycles |
6228d27738d1
target-utils: wait_ARM_cycles() added to libbase
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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18 wait_ARM_cycles: |
6228d27738d1
target-utils: wait_ARM_cycles() added to libbase
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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19 cmp r0, #0 |
6228d27738d1
target-utils: wait_ARM_cycles() added to libbase
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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20 bxeq lr |
495
06ad5e30e8d0
target-utils: wait_ARM_cycles() changed to 4 cycles per loop
Mychaela Falconia <falcon@freecalypso.org>
parents:
453
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21 1: subs r0, r0, #1 |
453
6228d27738d1
target-utils: wait_ARM_cycles() added to libbase
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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22 bne 1b |
6228d27738d1
target-utils: wait_ARM_cycles() added to libbase
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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23 bx lr |