annotate target-utils/lunadrv/haoran.c @ 1014:961efadd530a default tip

fc-shell TCH DL handler: add support for CSD modes TCH DL capture mechanism in FC Tourmaline firmware has been extended to support CSD modes in addition to speech - add the necessary support on the host tools side. It needs to be noted that this mechanism in its present state does NOT provide the debug utility value that was sought: as we learned only after the code was implemented, TI's DSP has a misfeature in that the buffer we are reading (a_dd_0[]) is zeroed out when the IDS block is enabled, i.e., we are reading all zeros and not the real DL bits we were after. But since the code has already been written, we are keeping it - perhaps we can do some tests with IDS disabled.
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 26 Nov 2024 06:27:43 +0000
parents db9a8e88e63f
children
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1 #include "types.h"
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2 #include "luna.h"
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3
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4 /*
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5 * ILI9225G register init for HaoRan HT020K1QC36S LCD.
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6 */
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7
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8 init_haoran()
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9 {
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10 /* reset pulse */
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11 CNTL_RST_REG |= EXT_RESET;
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12 wait_ARM_cycles(DELAY_1MS * 10);
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13 CNTL_RST_REG &= ~EXT_RESET;
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14 wait_ARM_cycles(DELAY_1MS * 50);
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15 /* start register init */
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16 LCD_REG_WR(0x0001, 0x011c); // set SS and NL bit
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17 LCD_REG_WR(0x0002, 0x0100); // set 1 line inversion
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18 LCD_REG_WR(0x0003, 0x1030); // set GRAM write direction and BGR=1.
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19 LCD_REG_WR(0x0008, 0x0808); // set BP and FP
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20 LCD_REG_WR(0x000F, 0x0901); // Set frame rate
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21 wait_ARM_cycles(DELAY_1MS * 10);
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22 LCD_REG_WR(0x0010, 0x0000); // Set SAP,DSTB,STB
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23 LCD_REG_WR(0x0011, 0x1B41); // Set APON,PON,AON,VCI1EN,VC
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24 wait_ARM_cycles(DELAY_1MS * 50);
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25 LCD_REG_WR(0x0012, 0x200E); // Internal reference voltage= Vci;
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26 LCD_REG_WR(0x0013, 0x0052); // Set GVDD
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27 LCD_REG_WR(0x0014, 0x4B5C); // Set VCOMH/VCOML voltage
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28 //------------- Set GRAM area ------------------//
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29 LCD_REG_WR(0x0030, 0x0000);
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30 LCD_REG_WR(0x0031, 0x00DB);
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31 LCD_REG_WR(0x0032, 0x0000);
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32 LCD_REG_WR(0x0033, 0x0000);
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33 LCD_REG_WR(0x0034, 0x00DB);
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34 LCD_REG_WR(0x0035, 0x0000);
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35 LCD_REG_WR(0x0036, 0x00AF);
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36 LCD_REG_WR(0x0037, 0x0000);
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37 LCD_REG_WR(0x0038, 0x00DB);
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38 LCD_REG_WR(0x0039, 0x0000);
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39 // ----------- Adjust the Gamma Curve ----------//
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40 LCD_REG_WR(0x0050, 0x0000);
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41 LCD_REG_WR(0x0051, 0x0705);
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42 LCD_REG_WR(0x0052, 0x0C0A);
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43 LCD_REG_WR(0x0053, 0x0401);
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44 LCD_REG_WR(0x0054, 0x040C);
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45 LCD_REG_WR(0x0055, 0x0608);
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46 LCD_REG_WR(0x0056, 0x0000);
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47 LCD_REG_WR(0x0057, 0x0104);
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48 LCD_REG_WR(0x0058, 0x0E06);
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49 LCD_REG_WR(0x0059, 0x060E);
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50 wait_ARM_cycles(DELAY_1MS * 50);
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51 LCD_REG_WR(0x0007, 0x1017);
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52 return(0);
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53 }