FreeCalypso > hg > freecalypso-tools
annotate loadtools/scripts/dsample.config @ 983:0407d14fb854
PL-J flash PPB ops: rework for full verification of lock state
| author | Mychaela Falconia <falcon@freecalypso.org> | 
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| date | Sat, 02 Dec 2023 08:22:00 +0000 | 
| parents | 49ee210fc4fb | 
| children | 
| rev | line source | 
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e7502631a0f9
initial import from freecalypso-sw rev 1033:5ab737ac3ad7
 Mychaela Falconia <falcon@freecalypso.org> parents: diff
changeset | 1 # The following parameters go into the <p command sent to the boot ROM | 
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initial import from freecalypso-sw rev 1033:5ab737ac3ad7
 Mychaela Falconia <falcon@freecalypso.org> parents: diff
changeset | 2 # The values to be used have been gleaned from the 20020917 fw image | 
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initial import from freecalypso-sw rev 1033:5ab737ac3ad7
 Mychaela Falconia <falcon@freecalypso.org> parents: diff
changeset | 3 | 
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initial import from freecalypso-sw rev 1033:5ab737ac3ad7
 Mychaela Falconia <falcon@freecalypso.org> parents: diff
changeset | 4 # CLKTCXO input is 13 MHz on the D-Sample, and with Calypso C05 | 
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initial import from freecalypso-sw rev 1033:5ab737ac3ad7
 Mychaela Falconia <falcon@freecalypso.org> parents: diff
changeset | 5 # the max allowed PLL'ed clock is 78 MHz for the DSP and 39 MHz for the ARM. | 
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e7502631a0f9
initial import from freecalypso-sw rev 1033:5ab737ac3ad7
 Mychaela Falconia <falcon@freecalypso.org> parents: diff
changeset | 6 # TI's firmware sets the PLL up to multiply by 6 (giving 78 MHz) with | 
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e7502631a0f9
initial import from freecalypso-sw rev 1033:5ab737ac3ad7
 Mychaela Falconia <falcon@freecalypso.org> parents: diff
changeset | 7 # divide by 2 for the ARM, but the boot ROM doesn't do the latter when | 
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e7502631a0f9
initial import from freecalypso-sw rev 1033:5ab737ac3ad7
 Mychaela Falconia <falcon@freecalypso.org> parents: diff
changeset | 8 # the input clock is 13 MHz. Hence we'll program the PLL to multiply | 
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e7502631a0f9
initial import from freecalypso-sw rev 1033:5ab737ac3ad7
 Mychaela Falconia <falcon@freecalypso.org> parents: diff
changeset | 9 # by 3, putting everything at 39 MHz. | 
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initial import from freecalypso-sw rev 1033:5ab737ac3ad7
 Mychaela Falconia <falcon@freecalypso.org> parents: diff
changeset | 10 | 
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initial import from freecalypso-sw rev 1033:5ab737ac3ad7
 Mychaela Falconia <falcon@freecalypso.org> parents: diff
changeset | 11 pll-config 3/1 | 
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initial import from freecalypso-sw rev 1033:5ab737ac3ad7
 Mychaela Falconia <falcon@freecalypso.org> parents: diff
changeset | 12 rhea-cntl 0x00 # set by 20020917 fw, hence presumed correct | 
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initial import from freecalypso-sw rev 1033:5ab737ac3ad7
 Mychaela Falconia <falcon@freecalypso.org> parents: diff
changeset | 13 | 
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initial import from freecalypso-sw rev 1033:5ab737ac3ad7
 Mychaela Falconia <falcon@freecalypso.org> parents: diff
changeset | 14 # The remaining settings are carried out via loadagent commands | 
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initial import from freecalypso-sw rev 1033:5ab737ac3ad7
 Mychaela Falconia <falcon@freecalypso.org> parents: diff
changeset | 15 init-script cs2-4ws-8mb.init | 
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initial import from freecalypso-sw rev 1033:5ab737ac3ad7
 Mychaela Falconia <falcon@freecalypso.org> parents: diff
changeset | 16 | 
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49ee210fc4fb
loadtools/scripts/*.config: new flash config
 Mychaela Falconia <falcon@freecalypso.org> parents: 
326diff
changeset | 17 # 8 MiB flash, accessible at 0x03000000 without any problems | 
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49ee210fc4fb
loadtools/scripts/*.config: new flash config
 Mychaela Falconia <falcon@freecalypso.org> parents: 
326diff
changeset | 18 flash single-8M 0x03000000 | 
| 0 
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initial import from freecalypso-sw rev 1033:5ab737ac3ad7
 Mychaela Falconia <falcon@freecalypso.org> parents: diff
changeset | 19 | 
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initial import from freecalypso-sw rev 1033:5ab737ac3ad7
 Mychaela Falconia <falcon@freecalypso.org> parents: diff
changeset | 20 # Perform a Iota poweroff when we are done | 
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initial import from freecalypso-sw rev 1033:5ab737ac3ad7
 Mychaela Falconia <falcon@freecalypso.org> parents: diff
changeset | 21 exit-mode iota-off | 
