# HG changeset patch # User Space Falcon # Date 1430017592 0 # Node ID fc713944bd1c1905f3e3e5597edfb50b3abb09e2 # Parent 9e54d153eb8c80cba6f3ce0f025a4c45e7d86c03 gsm-fw: uartfax.c included in the build with feature at-modem diff -r 9e54d153eb8c -r fc713944bd1c gsm-fw/cfgmagic/feature.at-modem --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/gsm-fw/cfgmagic/feature.at-modem Sun Apr 26 03:06:32 2015 +0000 @@ -0,0 +1,12 @@ +case $TARGET in + gtamodem) + ;; + *) + echo "Error: feature at-modem not supported on this target" 1>&2 + exit 1 + ;; +esac + +CONFIG_FDMODEM=1 +export_to_c CONFIG_FDMODEM +export_to_mk CONFIG_FDMODEM diff -r 9e54d153eb8c -r fc713944bd1c gsm-fw/serial/Makefile --- a/gsm-fw/serial/Makefile Sun Apr 26 01:27:29 2015 +0000 +++ b/gsm-fw/serial/Makefile Sun Apr 26 03:06:32 2015 +0000 @@ -2,7 +2,12 @@ CFLAGS= -O2 -fno-builtin -mthumb-interwork -mthumb LD= arm-elf-ld +sinclude ../include/config.mk + OBJS= debug.o init.o serialswitch.o uart.o +ifeq (${CONFIG_FDMODEM},1) +OBJS+= uartfax.o +endif HDRS= faxdata.h serialswitch.h traceswitch.h uart.h uartfax.h diff -r 9e54d153eb8c -r fc713944bd1c gsm-fw/serial/uartfax.c --- a/gsm-fw/serial/uartfax.c Sun Apr 26 01:27:29 2015 +0000 +++ b/gsm-fw/serial/uartfax.c Sun Apr 26 03:06:32 2015 +0000 @@ -76,24 +76,17 @@ * */ -#include "swconfig.cfg" - -#include "l1sw.cfg" - -#if (OP_L1_STANDALONE == 0) - #include "rv.cfg" -#endif -#include "board.cfg" -#include "chipset.cfg" -#ifdef BLUETOOTH_INCLUDED -#include "btemobile.cfg" -#endif - +#include "../include/config.h" #include -#include "nucleus.h" - -#include "main/sys_types.h" + +/* + * rv_general.h is needed for macros Min & Min3. + */ +#include "../riviera/rv/rv_general.h" +#include "../nucleus/nucleus.h" + +#include "../include/sys_types.h" #include "faxdata.h" #include "uartfax.h" @@ -104,23 +97,20 @@ #include "serialswitch.h" extern SYS_BOOL uart_sleep_timer_enabled; -/* - * rv_general.h is needed for macros Min & Min3. - */ - -#include "rv/rv_general.h" - -#include "memif/mem.h" - -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) - #include "armio/armio.h" +#include "../bsp/mem.h" +#include "../bsp/armio.h" + +#if CONFIG_TARGET_GTAMODEM + #define EXTHOST_WAKEUP_GPIO 1 +#else + #undef EXTHOST_WAKEUP_GPIO #endif /* * Maximal value for an unsigned 32 bits. */ -#define MAX_UNSIGNED_32 (4294967295) +#define MAX_UNSIGNED_32 (0xFFFFFFFFU) #define FIFO_SIZE (64) /* In bytes. */ @@ -305,27 +295,16 @@ #define RX_HISR_PRIORITY (2) - - - // NGENGE increase hisr stack otherwise overflows with multiple callbacks //#define RX_HISR_STACK_SIZE (512) /* Bytes. */ #define RX_HISR_STACK_SIZE (768) /* Bytes. */ - - - #define TX_HISR_PRIORITY (2) - - // NGENGE increase hisr stack otherwise overflows with multiple callbacks //#define TX_HISR_STACK_SIZE (512) /* Bytes. */ #define TX_HISR_STACK_SIZE (768) /* Bytes. */ - - - #define V24_HISR_PRIORITY (2) #define V24_HISR_STACK_SIZE (512) /* Bytes. */ @@ -356,12 +335,12 @@ *((volatile SYS_UWORD8 *) ((UART)->base_address + (REG))) = (VALUE) #define RESET_BIT(UART,REG,BIT) \ - (WRITE_UART_REGISTER ( \ - UART, REG, READ_UART_REGISTER (UART, REG) & ~(1 << (BIT)))) + (WRITE_UART_REGISTER ( \ + UART, REG, READ_UART_REGISTER (UART, REG) & ~(1 << (BIT)))) #define SET_BIT(UART,REG,BIT) \ - (WRITE_UART_REGISTER ( \ - UART, REG, READ_UART_REGISTER (UART, REG) | (1 << (BIT)))) + (WRITE_UART_REGISTER ( \ + UART, REG, READ_UART_REGISTER (UART, REG) | (1 << (BIT)))) /* @@ -553,7 +532,7 @@ SYS_UWORD8 rts_level; /* RTS on RS232 side, CTS on chipset side. 1: The RS232 line is deactivated (low). */ -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if TARGET_HAS_DTR_INPUT SYS_UWORD8 dtr_level; /* Controlled with an I/O on C & D-Sample and handled by Calypso+ on E-Sample. 1: The RS232 line is deactivated (low). */ @@ -657,7 +636,7 @@ static const SYS_UWORD8 dll[] = { - 0, /* Auto baud: */ + 0, /* Auto baud: */ 81, /* 75 baud. */ 40, /* 150 baud. */ 148, /* 300 baud. */ @@ -915,7 +894,7 @@ * lose events detected in the RX interrupt handler. */ -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if TARGET_HAS_DTR_INPUT if (call_source == 3) /* Call from Rx HISR */ dtr_level = uart->dtr_level_saved[uart->index_hisr]; else @@ -932,7 +911,7 @@ state |= ((((SYS_UWORD32) uart->rts_level) << RTS) | -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if TARGET_HAS_DTR_INPUT (((SYS_UWORD32) dtr_level) << DTR) | #endif @@ -955,7 +934,7 @@ * DTR is supported on C, D & E-Sample. */ -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if TARGET_HAS_DTR_INPUT state |= (((SYS_UWORD32) uart->dtr_level) << SA); #endif @@ -1800,27 +1779,26 @@ current_byte = first_byte; if (*bytes_in_rx_buffer) { - - - /* The Rx buffer is not empty and is being used by HISR ! */ - /* Hence stop the flow control */ + + /* The Rx buffer is not empty and is being used by HISR ! */ + /* Hence stop the flow control */ stop_receiver (uart); - /* - * Reset LCR[7] (DLAB) to have access to the RBR, THR and IER registers. - */ - WRITE_UART_REGISTER (uart, LCR, READ_UART_REGISTER (uart, LCR) & ~DLAB); - - /* Mask The Rx and interrupt */ + /* + * Reset LCR[7] (DLAB) to have access to the RBR, THR and IER registers. + */ + WRITE_UART_REGISTER (uart, LCR, READ_UART_REGISTER (uart, LCR) & ~DLAB); + + /* Mask The Rx and interrupt */ - WRITE_UART_REGISTER ( + WRITE_UART_REGISTER ( uart, IER, READ_UART_REGISTER (uart, IER) & ~(ERBI | EDSSI)); - uart->rx_stopped_by_lisr = 1; + uart->rx_stopped_by_lisr = 1; return (bytes_received); - - } + + } uart->rx_buffer_used_by_rx_lisr = first_byte; @@ -1965,7 +1943,7 @@ SER_restart_uart_sleep_timer (); uart_sleep_timer_enabled = 1; -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if TARGET_HAS_DTR_INPUT uart->index_hisr = (uart->index_hisr + 1) & 0x01; /* 0 or 1 */ #endif @@ -2090,7 +2068,7 @@ wrap_around_counter -= bytes_to_copy; if (!wrap_around_counter) - uart->rx_in = &(uart->rx_buffer[0]); + uart->rx_in = &(uart->rx_buffer[0]); else uart->rx_in += bytes_to_copy; @@ -2123,8 +2101,8 @@ /* * bytes_free_in_rx_buffer not updated since not used anymore. */ - bytes_read -= bytes_to_copy; - + bytes_read -= bytes_to_copy; + } else { bytes_read = 0; @@ -2166,7 +2144,7 @@ (uart->rd_call_setup == rm_reInstall))) { if ((bytes_in_rx_buffer >= uart->rx_threshold_level) || -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if TARGET_HAS_DTR_INPUT uart->dtr_change_detected[uart->index_hisr] || #endif uart->break_received || @@ -2179,7 +2157,7 @@ uart->reading_suspended = 0; uart->break_received = 0; uart->esc_seq_received = 0; -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if TARGET_HAS_DTR_INPUT uart->dtr_change_detected[uart->index_hisr] = 0; #endif } @@ -2188,7 +2166,6 @@ } - WRITE_UART_REGISTER (uart, LCR, READ_UART_REGISTER (uart, LCR) & ~DLAB); /* Mask The Rx and Modem status interrupt */ @@ -2499,11 +2476,9 @@ if (DRIVER_DISABLED (uart)) empty_rx_fifo (uart); - else if (build_rx_fifo_array (uart)){ + else if (build_rx_fifo_array (uart)) { (void) NU_Activate_HISR (&(uart->rx_hisr_ctrl_block)); - - } - + } } @@ -2592,7 +2567,9 @@ else { uart->tx_stopped_by_driver = 0; - LowGPIO(1); +#ifdef EXTHOST_WAKEUP_GPIO + AI_ResetBit(EXTHOST_WAKEUP_GPIO); +#endif #if ((CHIPSET != 5) && (CHIPSET != 6)) /* @@ -2999,7 +2976,7 @@ else uart->rts_level = 1; -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) +#if TARGET_HAS_DTR_INPUT /* * On C & D-Sample, 2 I/O are used to control DCD and DTR on UART Modem. * DCD: I/O 2 (output) @@ -3219,7 +3196,7 @@ WRITE_UART_REGISTER (uart, IER, 0x00); -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) +#if TARGET_HAS_DTR_INPUT AI_MaskIT (ARMIO_MASKIT_GPIO); #elif (CHIPSET == 12) DISABLE_DSR_INTERRUPT (uart); @@ -3360,7 +3337,7 @@ else uart->rts_level = 1; -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) +#if TARGET_HAS_DTR_INPUT /* * Read the state of DTR and select the edge. */ @@ -3944,8 +3921,8 @@ deep_sleep = 0; /* - * Check if RX & TX FIFOs are both empty - */ + * Check if RX & TX FIFOs are both empty + */ status = READ_UART_REGISTER (uart, LSR); @@ -4322,8 +4299,10 @@ /* If we have been stopped due to high RTS, we have to * wake up application processor by IRQ via IO1 -HW */ +#ifdef EXTHOST_WAKEUP_GPIO if (uart->tx_stopped_by_driver) - HighGPIO(1); + AI_SetBit(EXTHOST_WAKEUP_GPIO); +#endif /* * If: @@ -4544,7 +4523,7 @@ *state |= ((((SYS_UWORD32) uart->rts_level) << RTS) | -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if TARGET_HAS_DTR_INPUT (((SYS_UWORD32) uart->dtr_level) << DTR) | #endif @@ -4568,7 +4547,7 @@ * DTR is supported on C, D & E-Sample. */ -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if TARGET_HAS_DTR_INPUT *state |= (((SYS_UWORD32) uart->dtr_level) << SA); #endif @@ -4883,7 +4862,7 @@ case RX_DATA: -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) +#if TARGET_HAS_DTR_INPUT uart->index_it = (uart->index_it + 1) & 0x01; /* 0 or 1 */ uart->dtr_change_detected[uart->index_it] = 0; uart->dtr_level_saved[uart->index_it] = uart->dtr_level; @@ -4994,7 +4973,7 @@ /* * There is no case where FD_INTERNAL_ERR may be returned. - */ + */ result = FD_OK; @@ -5017,7 +4996,7 @@ return (result); } -#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) +#if TARGET_HAS_DTR_INPUT /******************************************************************************* * * UAF_DTRInterruptHandler @@ -5167,5 +5146,3 @@ return (FD_OK); } #endif /* (defined BTEMOBILE && (CHIPSET != 12)) */ - -