# HG changeset patch
# User Mychaela Falconia <falcon@ivan.Harhan.ORG>
# Date 1451707551 0
# Node ID c22afeecbf3435882c7f5b0fef03718e9c137d9f
# Parent  63ea60e7fbbc85b21acab2360eb0766034d11075
loadtools/scripts: D-Sample config added

diff -r 63ea60e7fbbc -r c22afeecbf34 loadtools/scripts/cs2-4ws-8mb.init
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/loadtools/scripts/cs2-4ws-8mb.init	Sat Jan 02 04:05:51 2016 +0000
@@ -0,0 +1,11 @@
+# This loadtool init script provides memory interface register setup
+# for targets which fit the following criteria:
+#
+# 3 chip selects are used: nCS0, nCS1 and nCS2
+# 4 wait states are to be used (register setting 00A4)
+# 8 MiB memory banks are in use, such that ADD22 needs to be enabled
+
+w16 fffffb00 00A4
+w16 fffffb02 00A4
+w16 fffffb04 00A4
+w16 fffef006 0008
diff -r 63ea60e7fbbc -r c22afeecbf34 loadtools/scripts/dsample.config
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/loadtools/scripts/dsample.config	Sat Jan 02 04:05:51 2016 +0000
@@ -0,0 +1,22 @@
+# The following parameters go into the <p command sent to the boot ROM
+# The values to be used have been gleaned from the 20020917 fw image
+
+# CLKTCXO input is 13 MHz on the D-Sample, and with Calypso C05
+# the max allowed PLL'ed clock is 78 MHz for the DSP and 39 MHz for the ARM.
+# TI's firmware sets the PLL up to multiply by 6 (giving 78 MHz) with
+# divide by 2 for the ARM, but the boot ROM doesn't do the latter when
+# the input clock is 13 MHz.  Hence we'll program the PLL to multiply
+# by 3, putting everything at 39 MHz.
+
+pll-config 3/1
+rhea-cntl 0x00		# set by 20020917 fw, hence presumed correct
+
+# The remaining settings are carried out via loadagent commands
+init-script cs2-4ws-8mb.init
+
+# 8 MiB flash, accessible at 0x03000000 without Compal-like problems,
+# let's use CFI.
+flash cfi-8M 0x03000000
+
+# Perform a Iota poweroff when we are done
+exit-mode iota-off