# HG changeset patch
# User Mychaela Falconia <falcon@ivan.Harhan.ORG>
# Date 1446609060 0
# Node ID 15b1b396ad23b93ed3765513bd561ebbe3f6c973
# Parent  eb27543ce18e254a31bb8761107ad659f9c4ed66
c139explore: OsmocomBB morons got uwire wrong, TI got it right

diff -r eb27543ce18e -r 15b1b396ad23 target-utils/c139explore/uwire.c
--- a/target-utils/c139explore/uwire.c	Wed Nov 04 03:03:38 2015 +0000
+++ b/target-utils/c139explore/uwire.c	Wed Nov 04 03:51:00 2015 +0000
@@ -63,30 +63,41 @@
 	while ((UWIRE_REGS.reg_csr & mask) != val);
 }
 
+/*
+ * Let's try changing the chip select logic from OsmocomBB way
+ * to the way seen in TI's R2D source.
+ */
+
 void uwire_init(void)
 {
 	UWIRE_REGS.reg_sr3 = UWIRE_SR3_CLK_EN | UWIRE_SR3_CLK_DIV2;
+	UWIRE_REGS.reg_sr1 = UWIRE_CSn_FRQ_DIV2;
+#if 0
 	UWIRE_REGS.reg_sr1 = UWIRE_CSn_CS_LVL | UWIRE_CSn_FRQ_DIV2;
 	UWIRE_REGS.reg_csr = UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD;
 	_uwire_wait(UWIRE_CSR_CSRB, 0);
+#endif
 }
 
 send_via_uwire(word)
 	unsigned word;
 {
-	u16 tmp = 0;
-
+#if 0
 	/* select the chip */
 	UWIRE_REGS.reg_csr = UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD;
 	_uwire_wait(UWIRE_CSR_CSRB, 0);
+#endif
 
 	UWIRE_REGS.reg_data = word << 7;
-	UWIRE_REGS.reg_csr = UWIRE_CSR_BITS_WR(9) | UWIRE_CSR_START;
+	UWIRE_REGS.reg_csr = UWIRE_CSR_BITS_WR(9) | UWIRE_CSR_START
+				| UWIRE_CSR_CS_CMD;
 	_uwire_wait(UWIRE_CSR_CSRB, 0);
 
 	/* unselect the chip */
 	UWIRE_REGS.reg_csr = UWIRE_CSR_IDX(0) | 0;
+#if 0
 	_uwire_wait(UWIRE_CSR_CSRB, 0);
+#endif
 
 	return 0;
 }