# HG changeset patch
# User Mychaela Falconia <falcon@ivan.Harhan.ORG>
# Date 1445274836 0
# Node ID 10b4bed101927563438be7c721fd884aae3149aa
# Parent  fb3f04a62f71f696eac4371e6dbfa5799220115c
gsm-fw/L1: fix for the DSP patch corruption bug

The L1 code we got from the LoCosto fw contains a feature for DSP CPU load
measurement.  This feature is a LoCosto-ism, i.e., not applicable to earlier
DBB chips (Calypso) with their respective earlier DSP ROMs.  Most of the
code dealing with that feature is conditionalized as #if (DSP >= 38),
but one spot was missed, and the MCU code was writing into an API word
dealing with this feature.  In TCS211 this DSP API word happens to be
used by the DSP code patch, hence that write was corrupting the patched
DSP code.

diff -r fb3f04a62f71 -r 10b4bed10192 gsm-fw/L1/cfile/l1_drive.c
--- a/gsm-fw/L1/cfile/l1_drive.c	Mon Oct 19 04:10:34 2015 +0000
+++ b/gsm-fw/L1/cfile/l1_drive.c	Mon Oct 19 17:13:56 2015 +0000
@@ -1115,8 +1115,10 @@
     // Enable frame IT on next TDMA
     l1dmacro_set_frame_it();
 
+    #if (DSP >= 38)
     // DSP CPU load measurement - write logic (provide TDMA frame number to DSP)
     (*((volatile UWORD16 *)(DSP_CPU_LOAD_MCU_W_TDMA_FN))) = (API)l1s.actual_time.fn_mod42432;
+    #endif
 
   #endif // NOT_SIMULATION
 }
diff -r fb3f04a62f71 -r 10b4bed10192 gsm-fw/L1/include/l1_const.h
--- a/gsm-fw/L1/include/l1_const.h	Mon Oct 19 04:10:34 2015 +0000
+++ b/gsm-fw/L1/include/l1_const.h	Mon Oct 19 17:13:56 2015 +0000
@@ -1697,12 +1697,14 @@
       #define DB2_R_PAGE_1       0xFFD00188L
     #endif
 
-    /* DSP CPU load measurement */
-    #define DSP_CPU_LOAD_MCU_API_BASE_ADDRESS 0xFFD01DE0L
-    #define DSP_CPU_LOAD_DB_W_PAGE_0          0xFFD01DE0L   // DB page 0 write : 4 words long
-    #define DSP_CPU_LOAD_DB_W_PAGE_1          0xFFD01DE8L   // DB page 1 write : 4 words long
-    #define DSP_CPU_LOAD_MCU_W_CTRL           0xFFD01DF0L   // DSP CPU load feature control
-    #define DSP_CPU_LOAD_MCU_W_TDMA_FN        0xFFD01DF2L   // MCU TDMA frame number
+    #if (DSP >= 38)
+      /* DSP CPU load measurement */
+      #define DSP_CPU_LOAD_MCU_API_BASE_ADDRESS 0xFFD01DE0L
+      #define DSP_CPU_LOAD_DB_W_PAGE_0          0xFFD01DE0L   // DB page 0 write : 4 words long
+      #define DSP_CPU_LOAD_DB_W_PAGE_1          0xFFD01DE8L   // DB page 1 write : 4 words long
+      #define DSP_CPU_LOAD_MCU_W_CTRL           0xFFD01DF0L   // DSP CPU load feature control
+      #define DSP_CPU_LOAD_MCU_W_TDMA_FN        0xFFD01DF2L   // MCU TDMA frame number
+    #endif
 
   #else
     #define MCU_API_BASE_ADDRESS 0xFFD00000L