FreeCalypso > hg > freecalypso-sw

comparison gsm-fw/services/ffs/drv.c @ 941:6b0b2f6dbb20

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gsm-fw/services/ffs/drv.c: AMD multi-bank flash driver fixed for Pirelli and future FreeCalypso hardware
author Mychaela Falconia <falcon@ivan.Harhan.ORG>
date Sun, 01 Nov 2015 00:07:09 +0000
parents 0fb9b7f2ef87
children
comparison
equal deleted inserted replaced
940:0fb9b7f2ef87 941:6b0b2f6dbb20
207 void ffsdrv_amd_write_end(void); 207 void ffsdrv_amd_write_end(void);
208 void ffsdrv_amd_erase_end(void); 208 void ffsdrv_amd_erase_end(void);
209 209
210 void ffsdrv_amd_write_halfword(volatile uint16 *addr, uint16 value) 210 void ffsdrv_amd_write_halfword(volatile uint16 *addr, uint16 value)
211 { 211 {
212 volatile char *flash = dev.base; 212 volatile uint16 *flash = (volatile uint16 *)dev.base;
213 uint32 cpsr; 213 uint32 cpsr;
214 214
215 tlw(led_on(LED_WRITE)); 215 tlw(led_on(LED_WRITE));
216 ttw(ttr(TTrDrvWrite, "wh(%x,%x)" NL, addr, value)); 216 ttw(ttr(TTrDrvWrite, "wh(%x,%x)" NL, addr, value));
217 217
224 } 224 }
225 225
226 cpsr = int_disable(); 226 cpsr = int_disable();
227 tlw(led_toggle(LED_WRITE_SUSPEND)); 227 tlw(led_toggle(LED_WRITE_SUSPEND));
228 dev.state = DEV_WRITE; 228 dev.state = DEV_WRITE;
229 flash[0xAAAA] = 0xAA; // unlock cycle 1 229 flash[0x555] = 0xAA; // unlock cycle 1
230 flash[0x5555] = 0x55; // unlock cycle 2 230 flash[0x2AA] = 0x55; // unlock cycle 2
231 flash[0xAAAA] = 0xA0; 231 flash[0x555] = 0xA0;
232 *addr = value; 232 *addr = value;
233 int_enable(cpsr); 233 int_enable(cpsr);
234 tlw(led_toggle(LED_WRITE_SUSPEND)); 234 tlw(led_toggle(LED_WRITE_SUSPEND));
235 235
236 ffsdrv_amd_write_end(); 236 ffsdrv_amd_write_end();
272 tlw(led_off(LED_WRITE)); 272 tlw(led_off(LED_WRITE));
273 } 273 }
274 274
275 void ffsdrv_amd_erase(uint8 block) 275 void ffsdrv_amd_erase(uint8 block)
276 { 276 {
277 volatile char *flash = dev.base; 277 volatile uint16 *flash = (volatile uint16 *)dev.base;
278 uint32 cpsr; 278 uint32 cpsr;
279 279
280 tlw(led_on(LED_ERASE)); 280 tlw(led_on(LED_ERASE));
281 ttw(ttr(TTrDrvErase, "e(%d)" NL, block)); 281 ttw(ttr(TTrDrvErase, "e(%d)" NL, block));
282 282
283 dev.addr = (uint16 *) block2addr(block); 283 dev.addr = (uint16 *) block2addr(block);
284 284
285 cpsr = int_disable(); 285 cpsr = int_disable();
286 dev.state = DEV_ERASE; 286 dev.state = DEV_ERASE;
287 flash[0xAAAA] = 0xAA; // unlock cycle 1 287 flash[0x555] = 0xAA; // unlock cycle 1
288 flash[0x5555] = 0x55; // unlock cycle 2 288 flash[0x2AA] = 0x55; // unlock cycle 2
289 flash[0xAAAA] = 0x80; 289 flash[0x555] = 0x80;
290 flash[0xAAAA] = 0xAA; // unlock cycle 1 290 flash[0x555] = 0xAA; // unlock cycle 1
291 flash[0x5555] = 0x55; // unlock cycle 2 291 flash[0x2AA] = 0x55; // unlock cycle 2
292 *dev.addr = 0x30; // AMD erase sector command 292 *dev.addr = 0x30; // AMD erase sector command
293 int_enable(cpsr); 293 int_enable(cpsr);
294 294
295 ffsdrv_amd_erase_end(); 295 ffsdrv_amd_erase_end();
296 } 296 }