freecalypso-sw: gsm-fw/L1/include/leo-based/l1

annotate gsm-fw/L1/include/leo-based/l1_confg.h @ 992:a7b0b426f9ca

target-utils: boot ROM UART autodetection revamped The new implementation should work with both the familiar Calypso C035 boot ROM version found in our regular targets as well as the older Calypso F741979B version found on the vintage D-Sample board.

author	Mychaela Falconia <falcon@ivan.Harhan.ORG>
date	Wed, 30 Dec 2015 21:28:41 +0000
parents	25a7fe25864c
children

rev	line source
115 1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	1 /*********** Revision Controle System Header ***********
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	2 * GSM Layer 1 software
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	3 * L1_CONFG.H
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	4 *
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	5 * Filename l1_confg.h
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	6 * Copyright 2003 (C) Texas Instruments
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	7 *
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	8 *********** Revision Controle System Header ***********/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	9
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	10 #ifndef __L1_CONFG_H__
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	11 #define __L1_CONFG_H__
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	12
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	13 // Traces...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	14 // TRACE_TYPE == 1,2,3 are used in standalone mode (L2-L3 Simul) with USART
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	15 // TRACE_TYPE == 4 is used on A-sample only (with UART): L1 + protocol stack
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	16 // TRACE_TYPE == 1 -> L1/L3 interface trace
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	17 // TRACE_TYPE == 2 -> Trace mode: ~33~~1~011...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	18 // TRACE_TYPE == 3 -> same as above (2) plus FER or stats trace
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	19 // TRACE_TYPE == 4 -> L1/L3 interface trace on A-sample with protocol stack
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	20 // TRACE_TYPE == 5 -> trace for full simulation
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	21 // TRACE_TYPE == 6 -> CPU load trace for hisr
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	22 // TRACE_TYPE == 7 -> CPU LOAD trace for layer 1 hisr for all TDMA. Output on
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	23 // UART at 38400 bps =>
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	24 // format : <hisr cpu value in microseconds> <frame number>
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	25
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	26 // Code PB reported workaround
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	27 //------------------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	28
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	29
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	30 // Code Version possible choices
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	31 //------------------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	32 #define SIMULATION 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	33 #define NOT_SIMULATION 2
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	34
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	35 // RCL functions Version possible choices
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	36 //------------------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	37 #define POLL_FORCED 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	38 #define RLC_SCENARIO 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	39 #define MODEM_FLOW 2
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	40
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	41 // possible choices for UART trace output
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	42 //------------------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	43 #define MODEM_UART 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	44 #define IRDA_UART 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	45 #if (CHIPSET == 12)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	46 #define MODEM2_UART 2
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	47 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	48
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	49 //============
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	50 // CODE CHOICE
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	51 //============
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	52 #if 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	53 #if (OP_L1_STANDALONE==0)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	54 #define CODE_VERSION NOT_SIMULATION
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	55 #else // OP_L1_STANDALONE
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	56 #ifdef WIN32
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	57 #define CODE_VERSION SIMULATION
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	58 #else // WIN32
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	59 #define CODE_VERSION NOT_SIMULATION
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	60 #endif // WIN32
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	61 #endif // OP_L1_STANDALONE
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	62 #endif // #if 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	63
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	64 /* FreeCalypso */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	65 #define CODE_VERSION NOT_SIMULATION
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	66 #define AMR 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	67 #define L1_12NEIGH 1
526 80ee7eacdaeb L1 configuration: try a cut-down version first Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 522 diff changeset	68 #define L1_DYN_DSP_DWNLD 0 /* for now */
115 1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	69 #define L1_EOTD 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	70 #define L1_GTT 0
522 2c9c2b95ddec FC version of l1_rf12.c compiles Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 151 diff changeset	71 #define ORDER2_TX_TEMP_CAL 1
150 3c850b416c9a integrating more L1 header files needed by the abb+spi code Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 143 diff changeset	72 #define TRACE_TYPE 4
151 d0de2d0a426d more L1 header files brought in Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 150 diff changeset	73 #define VCXO_ALGO 1
115 1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	74
526 80ee7eacdaeb L1 configuration: try a cut-down version first Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 522 diff changeset	75 /* TESTMODE will be enabled with feature l1tm */
80ee7eacdaeb L1 configuration: try a cut-down version first Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 522 diff changeset	76
80ee7eacdaeb L1 configuration: try a cut-down version first Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 522 diff changeset	77 #if CONFIG_AUDIO
80ee7eacdaeb L1 configuration: try a cut-down version first Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 522 diff changeset	78 # define AUDIO_TASK 1 // Enable the L1 audio features
80ee7eacdaeb L1 configuration: try a cut-down version first Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 522 diff changeset	79 # define MELODY_E2 1
80ee7eacdaeb L1 configuration: try a cut-down version first Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 522 diff changeset	80 #endif
80ee7eacdaeb L1 configuration: try a cut-down version first Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 522 diff changeset	81
115 1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	82 #if CONFIG_GPRS
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	83 # define L1_GPRS 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	84 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	85 # define L1_GPRS 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	86 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	87
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	88 //---------------------------------------------------------------------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	89 // Test with full simulation.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	90 //---------------------------------------------------------------------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	91 #if (CODE_VERSION == SIMULATION)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	92
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	93 // Test Scenari...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	94 #define SCENARIO_FILE 1 // Test Scenario comes from input files.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	95 #define SCENARIO_MEM 0 // Test Scenario comes from RAM.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	96
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	97 // Traces...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	98 #undef TRACE_TYPE
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	99 #define TRACE_TYPE 5
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	100 #define LOGFILE_TRACE 1 // trace in an output logfile
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	101 #define FLOWCHART 0 // Message sequence/flow chart trace.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	102 #define NUCLEUS_TRACE 0 // Nucleus error trace
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	103 #define EOTD_TRACE 1 // EOTD log trace
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	104 #define TRACE_FULL_NAME 0 // display full fct names after a PM/COM error
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	105
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	106 #define L2_L3_SIMUL 1 // Layer 2 & Layer 3 simulated, main within NU_MAIN.C, trace possible.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	107
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	108 // Control algorithms...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	109 #define AFC_ALGO 1 // AFC algorithm.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	110 #define TOA_ALGO 1 // TOA algorithm.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	111 #define AGC_ALGO 1 // AGC algorithm.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	112 #define TA_ALGO 0 // TA (Timing Advance) algorithm.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	113 #undef VCXO_ALGO
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	114 #define VCXO_ALGO 0 // VCXO algo
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	115 #undef DCO_ALGO
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	116 #define DCO_ALGO 0 // DCO algo (TIDE)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	117 #undef ORDER2_TX_TEMP_CAL
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	118 #define ORDER2_TX_TEMP_CAL 0 // TX Temperature Compensation Algorithm selection
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	119
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	120
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	121 #define FACCH_TEST 0 // FACCH test enabled.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	122
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	123 #define ADC_TIMER_ON 0 // Timer for ADC measurements
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	124 #define AFC_ON 1 // Enable of the Omega AFC module
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	125
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	126 #define AUDIO_TASK 1 // Enable the L1 audio features
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	127 #define AUDIO_SIMULATION 1 // Audio simulator for the audio tasks (works only with the new audio design i.e. AUDIO_TASK=1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	128 #define AUDIO_L1_STANDALONE 0 // Flag to enable the audio simulator used with the L1 stand-alone (works only with the new audio design i.e. AUDIO_TASK=1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	129
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	130 #define GTT_SIMULATION 1 // Gtt simulator for the gtt tasks (works only with if L1_GTT=1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	131 #define TTY_SYNC_MCU 1 // TTY WORKAROUND BUG03401
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	132 #define TTY_SYNC_MCU_2 1 //
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	133 #define L1_GTT_FIFO_TEST_ATOMIC 0 //
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	134 #define NEW_WKA_PATCH 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	135 #define OPTIMISED 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	136
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	137 #define L1_RECOVERY 0 // L1 recovery
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	138
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	139 #undef L1_GPRS
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	140 #define L1_GPRS 1 // GPRS L1: MS supporting both Circuit Switched and Packet (GPRS) capabilities
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	141
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	142 #undef AMR
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	143 #define AMR 1 // AMR version 1.0 supported
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	144
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	145 #undef L1_12NEIGH
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	146 #define L1_12NEIGH 1 // new L1-RR interface for 12 neighbour cells
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	147
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	148 #undef L1_GTT
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	149 #define L1_GTT 1 // Enable Global Text Telephony feature for simulation
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	150
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	151 #undef OP_L1_STANDALONE
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	152 #define OP_L1_STANDALONE 1 // Selection of code for L1 stand alone
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	153
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	154 #undef OP_RIV_AUDIO
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	155 #define OP_RIV_AUDIO 0 // Selection of code for Riviera audio
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	156
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	157 #undef OP_WCP
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	158 #define OP_WCP 0 // No WCP integration
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	159 //---------------------------------------------------------------------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	160 // Test with H/W platform.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	161 //---------------------------------------------------------------------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	162 #elif (CODE_VERSION == NOT_SIMULATION)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	163
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	164 #define WA_PCTM_AGC_PARAMS 0 // to work by default with 4 parameters to calibration (compatible with PCTM if 1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	165 // Work around about Calypso RevA: the bus is floating (Cf PB01435)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	166 // (corrected with Calypso ReV B and Calypso C035)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	167 #if (CHIPSET == 7)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	168 #define W_A_CALYPSO_BUG_01435 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	169 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	170 #define W_A_CALYPSO_BUG_01435 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	171 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	172
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	173
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	174 // for AMR thresolds definition CQ22226
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	175 #define AMR_THRESHOLDS_WORKAROUND 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	176
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	177 #if (L1_GTT==1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	178 #define TTY_SYNC_MCU 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	179 #define TTY_SYNC_MCU_2 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	180 #define L1_GTT_FIFO_TEST_ATOMIC 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	181 #define NEW_WKA_PATCH 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	182 #define OPTIMISED 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	183 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	184 #define TTY_SYNC_MCU_2 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	185 #define L1_GTT_FIFO_TEST_ATOMIC 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	186 #define TTY_SYNC_MCU 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	187 #define NEW_WKA_PATCH 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	188 #define OPTIMISED 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	189
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	190 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	191
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	192 // Traces...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	193 #define NUCLEUS_TRACE 0 // Nucleus error trace
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	194 #define FLOWCHART 0 // Message sequence/flow chart trace.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	195 #define LOGFILE_TRACE 0 // trace in an output logfile
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	196 #define TRACE_FULL_NAME 0 // display full fct names after a PM/COM error
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	197
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	198 // Test Scenari...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	199 #define SCENARIO_FILE 0 // Test Scenario comes from input files.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	200 #define SCENARIO_MEM 1 // // Test Scenario comes from RAM.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	201
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	202 #if (OP_L1_STANDALONE == 1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	203 #define L2_L3_SIMUL 1 // Layer 2 & Layer 3 simulated, main within NU_MAIN.C, trace possible.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	204 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	205 #define L2_L3_SIMUL 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	206 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	207
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	208 // Control algorithms...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	209 #define AFC_ALGO 1 // AFC algorithm.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	210 //TOA Algorithm needs to be on for TestMode, otherwise no dedic test will be succesful!!!
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	211 #define TOA_ALGO 1 // TOA algorithm.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	212 #define AGC_ALGO 1 // AGC algorithm.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	213 #define TA_ALGO 1 // TA (Timing Advance) algorithm.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	214
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	215 #define FACCH_TEST 0 // FACCH test enabled.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	216
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	217 #define ADC_TIMER_ON 0 // Timer for ADC measurements
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	218 #define AFC_ON 1 // Enable of the Omega AFC module
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	219
526 80ee7eacdaeb L1 configuration: try a cut-down version first Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 522 diff changeset	220 #if 0
80ee7eacdaeb L1 configuration: try a cut-down version first Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 522 diff changeset	221 /* FreeCalypso: moved to config section above */
115 1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	222 #define AUDIO_TASK 1 // Enable the L1 audio features
526 80ee7eacdaeb L1 configuration: try a cut-down version first Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 522 diff changeset	223 #endif
115 1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	224 #define AUDIO_SIMULATION 0 // Audio simulator for the audio tasks (works only with the new audio design i.e. AUDIO_TASK=1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	225 #if (OP_L1_STANDALONE == 1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	226 #define AUDIO_L1_STANDALONE 1 // Flag to enable the audio simulator used with the L1 stand-alone (works only with the new audio design i.e. AUDIO_TASK=1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	227 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	228 #define AUDIO_L1_STANDALONE 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	229 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	230
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	231 #define GTT_SIMULATION 0 // Gtt simulator for the gtt tasks (works only with if L1_GTT=1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	232
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	233 #define OP_BT 0 // Simulation of ISLAND (BLUETOOTH) sleep management
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	234
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	235 #define L1_RECOVERY 1 // L1 recovery
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	236
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	237
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	238 #if (L1_GPRS == 1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	239 #define RLC_VERSION RLC_SCENARIO
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	240 #if (RLC_VERSION == RLC_SCENARIO)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	241 #define RLC_DL_BLOCK_STAT 0 // Works with RLC_VERSION = RLC_SCENARIO
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	242 // output stat on CRC error blocks
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	243 // The user must enter the cs type and
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	244 // the number of frames desired.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	245 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	246 #define RLC_DL_BLOCK_STAT 0 // Default value; Never change it
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	247 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	248
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	249 #if (OP_L1_STANDALONE == 1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	250 #define DSP_BACKGROUND_TASKS 1 // Enable the TEST of DSP background.tasks
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	251 // activated by a layer 3 message (BG_TASK_START (<task number>))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	252 // deactivated by a layer 3 message (BG_TASK_STOP (<task number>))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	253 // Warning : Works only with DSP>=31
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	254 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	255 #define DSP_BACKGROUND_TASKS 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	256 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	257
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	258 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	259 #define DSP_BACKGROUND_TASKS 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	260 #define RLC_DL_BLOCK_STAT 0 // Default value; Never change it
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	261 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	262 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	263
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	264 // Audio tasks selection
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	265 //-----------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	266
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	267 #if (AUDIO_TASK == 1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	268 #define KEYBEEP 1 // Enable keybeep feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	269 #define TONE 1 // Enable tone feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	270 // Temporary modification for protocol stack compatibility - GSMLITE will be removed
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	271 #if (OP_L1_STANDALONE == 1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	272 #define GSMLITE 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	273 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	274 #if ((OP_L1_STANDALONE == 1) \|\| (!GSMLITE))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	275 #define MELODY_E1 1 // Enable melody format E1 feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	276 #define VOICE_MEMO 1 // Enable voice memorization feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	277
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	278 #define FIR 1 // Enable FIR feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	279 #if (DSP == 33) \|\| (DSP == 34) \|\| (DSP == 35) \|\| (DSP == 36)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	280 #define AUDIO_MODE 1 // Enable Audio mode feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	281 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	282 #define AUDIO_MODE 0 // Disable Audio mode feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	283 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	284 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	285 #define MELODY_E1 0 // Disable melody format E1 feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	286 #define VOICE_MEMO 0 // Disable voice memorization feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	287 #if (MELODY_E2)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	288 #define FIR 1 // Enable FIR feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	289 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	290 #define FIR 0 // Disable FIR feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	291 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	292
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	293 #define AUDIO_MODE 0 // Disable Audio mode feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	294 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	295 // Define CPORT for ESample only
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	296 #if ((CHIPSET == 12) && ((DSP == 35) \|\| (DSP == 36)))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	297 #define L1_CPORT 1 // Enable cport feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	298 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	299 #define L1_CPORT 0 // Disable cport feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	300 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	301
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	302 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	303 #define KEYBEEP 0 // Enable keybeep feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	304 #define TONE 0 // Enable tone feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	305 #define MELODY_E1 0 // Enable melody format E1 feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	306 #define VOICE_MEMO 0 // Enable voice memorization feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	307
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	308 #define FIR 0 // Enable FIR feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	309 #define AUDIO_MODE 0 // Enable Audio mode feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	310 #define L1_CPORT 0 // Enable cport feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	311 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	312
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	313 #define L1_AUDIO_BACKGROUND_TASK (SPEECH_RECO \| MELODY_E2) // audio background task is used by speech reco and melody_e2
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	314 #if (OP_RIV_AUDIO == 1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	315 #define L1_AUDIO_DRIVER L1_VOICE_MEMO_AMR // Riviera audio driver (only Voice Memo AMR is available)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	316 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	317
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	318
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	319 // Vocoder selections
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	320 //-------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	321
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	322 #define FR 1 // Full Rate
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	323 #define FR_HR 2 // Full Rate + Half Rate
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	324 #define FR_EFR 3 // Full Rate + Enhanced Full Rate
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	325 #define FR_HR_EFR 4 // Full Rate + Half Rate + Enhanced Full Rate
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	326
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	327 // Standard (frequency plan) selections
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	328 //-------------------------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	329
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	330 #define GSM 1 // GSM900.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	331 #define GSM_E 2 // GSM900 Extended.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	332 #define PCS1900 3 // PCS1900.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	333 #define DCS1800 4 // DCS1800.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	334 #define DUAL 5 // Dual Band (GSM900 + DCS 1800 bands)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	335 #define DUALEXT 6 // Dual Band (E-GSM900 + DCS 1800 bands)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	336 #define GSM850 7 // GSM850 Band
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	337 #define DUAL_US 8 // PCS1900 + GSM850
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	338
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	339 /------------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	340 /* Power Management */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	341 /------------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	342 #define PWR_MNGT 1 // POWER management active if l1_config.pwr_mngt=1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	343
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	344
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	345 /---------------------------------------------------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	346 /* DSP configurations */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	347 /* ------------------ */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	348 /* DSP \| FR\| HR\|EFR\|14.4\| SPEED \|12LA68\|12LA68 \|4L32\|AEC\| MCU/DSP */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	349 /* (version) \| \| \| \| \| \|POLE80\|POLE112\| \|/NS\| interface */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	350 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	351 /* 0 (821) \| x \| \| \| \| 39Mhz \| x \| \| \| \| 1 */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	352 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	353 /* 1 (830) \| x \| \| \| \| 39Mhz \| (1) \| \| x \| \| 1 */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	354 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	355 /* 2 (912) \| x \| x \| \| \| 58.5Mhz \| x \| \| \| \| 2 */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	356 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	357 /* 3 (10xx) \| x \| \| x \| x \| 65Mhz \| x \| \| \| x \| 3 */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	358 /* ----------+---+---+---+----+---------+------+-------+----\|---+---------- */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	359 /* 4 (11xx) \| x \| x \| x \| x \| 65Mhz \| x \| x (3)\| \| x \| 3 */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	360 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	361 /* 5 (830) \| x \| \| \| \| 39Mhz \| x \| \| \| \| 1 */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	362 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	363 /* 6 (11xx) \| x \| x \| x \| x \| 65Mhz \| x \| x (3)\| \|(2)\| 3 */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	364 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	365 /* */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	366 /(1) this version can be loaded on a 12LA68/POLE80 but the RIF/DL problem is/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	367 /* not corrected. */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	368 /* */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	369 /(2) AEC is disabled at DSP level but L1 must be compiled with MCU/DSP /
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	370 /* interface which support AEC, therefore AEC is defined as 1. */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	371 /* */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	372 /(3) Pole112 include RIF DL correction. No patch is needed if this one only /
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	373 /* include RIF/DL problem. */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	374 /* */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	375 /---------------------------------------------------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	376 #if (DSP == 16 \|\| DSP == 17)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	377
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	378 /* #define CLKMOD1 0x414e // ...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	379 #define CLKMOD2 0x414e // ...65 Mips
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	380 #define CLKSTART 0x29 // ...65 Mips */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	381
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	382 #define CLKMOD1 0x4006 // ...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	383 #define CLKMOD2 0x4116 // ...65 Mips pll free
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	384 #define CLKSTART 0x29 // ...65 Mips
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	385
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	386 /* #define CLKMOD1 0x2116 //This settings force the DSP to never enteridle
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	387 #define CLKMOD2 0x2116 //In this case the PLL will be always on. 39 Mips
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	388 #define CLKSTART 0x25 // ...39 Mips */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	389
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	390 #define VOC FR_HR_EFR // FR + HR + EFR.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	391 #define DATA14_4 1 // No 14.4 data allowed.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	392 #define AEC 1 // AEC/NS supported.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	393 #define MAP 3
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	394 #define DSP_START 0x2000
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	395 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	396
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	397 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	398
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	399 /* DSP debug trace configuration */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	400 /-------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	401 #if (MELODY_E2)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	402 // In case of the melody E2 the DSP trace must be disable because the
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	403 // melody instrument waves are overlayed with DSP trace buffer
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	404
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	405 // DSP debug trace API buufer config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	406 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	407 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	408 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	409 // DSP debug trace API buufer config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	410 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	411 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	412 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	413
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	414 #elif (DSP == 30) // First GPRS.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	415 #define CLKMOD1 0x4006 // ...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	416 #define CLKMOD2 0x4116 // ...65 Mips pll free
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	417 #define CLKSTART 0x29 // ...65 Mips
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	418
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	419 #define VOC FR_HR_EFR // FR + HR + EFR.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	420 #define DATA14_4 1 // No 14.4 data allowed.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	421 #define AEC 1 // AEC/NS not supported.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	422 #define MAP 3
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	423 #define DSP_START 0x1F81
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	424 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	425 #define ULYSSE 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	426
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	427 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	428 #elif (DSP == 31) // ROM Code GPRS G0.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	429 #define CLKMOD1 0x4006 // ...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	430 #define CLKMOD2 0x4116 // ...65 Mips pll free
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	431 #define CLKSTART 0x29 // ...65 Mips
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	432
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	433 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	434 #define DATA14_4 1 // 14.4 data allowed.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	435 #define AEC 1 // AEC/NS not supported.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	436 #define MAP 3
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	437
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	438 #define DSP_START 0x8763
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	439
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	440 #define INSTALL_ADD 0x87c9 // Used to set gprs_install_address pointer
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	441 #define INSTALL_ADD_WITH_PATCH 0x1352 // Used to set gprs_install_address pointer
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	442
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	443 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	444 #define ULYSSE 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	445
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	446 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	447 #elif (DSP == 32) // ROM Code GPRS G1.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	448 #define CLKMOD1 0x4006 // ...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	449 #define CLKMOD2 0x4116 // ...65 Mips pll free
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	450 #define CLKSTART 0x29 // ...65 Mips
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	451
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	452 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	453 #define DATA14_4 1 // 14.4 data allowed.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	454 #define AEC 1 // AEC/NS not supported.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	455 #define MAP 3
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	456
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	457 #define DSP_START 0x8763
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	458
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	459 #define INSTALL_ADD 0x87c9 // Used to set gprs_install_address pointer
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	460
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	461 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	462 #define ULYSSE 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	463
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	464 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	465 #elif (DSP == 33) // ROM Code GPRS.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	466 #define CLKMOD1 0x4006 // ...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	467 #define CLKMOD2 0x4116 // ...65 Mips pll free
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	468 #define CLKSTART 0x29 // ...65 Mips
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	469 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	470 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	471 #define AEC 1 // AEC/NS not supported.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	472 #if (OP_RIV_AUDIO == 0)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	473 #define L1_NEW_AEC 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	474 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	475 // Available but not yet tuned with Riviera AUDIO
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	476 #define L1_NEW_AEC 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	477 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	478 #if ((L1_NEW_AEC) && (!AEC))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	479 // First undef the flag to avoid warnings at compilation time
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	480 #undef AEC
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	481 #define AEC 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	482 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	483
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	484 #define MAP 3
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	485
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	486 #define DSP_START 0x7000
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	487
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	488 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	489
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	490 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	491 #define ULYSSE 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	492
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	493 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	494
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	495 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	496
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	497 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	498
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	499 // management.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	500
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	501 // DSP_IDLE3 is not supported in simulation
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	502
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	503 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	504 #define W_A_DSP_IDLE3 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	505 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	506
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	507 // DSP software work-around config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	508 // bit0 - Work-around to support CRTG.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	509 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	510 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	511 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	512
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	513 #if (ANALOG == 1) // OMEGA / NAUSICA
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	514 #define C_DSP_SW_WORK_AROUND 0x0006
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	515
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	516 #elif (ANALOG == 2) // IOTA
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	517 #define C_DSP_SW_WORK_AROUND 0x000E
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	518
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	519 #elif (ANALOG == 3) // SYREN
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	520 #define C_DSP_SW_WORK_AROUND 0x000E
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	521
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	522 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	523
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	524 /* DSP debug trace configuration */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	525 /-------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	526 #if (MELODY_E2)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	527 // In case of the melody E2 the DSP trace must be disable because the
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	528 // melody instrument waves are overlayed with DSP trace buffer
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	529
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	530 // DSP debug trace API buufer config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	531 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	532 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	533
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	534 // DSP debug trace type config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	535 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	536 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	537 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	538
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	539 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	540 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	541 // Currently not supported !
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	542 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	543 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	544 // DSP debug trace API buufer config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	545 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	546 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	547
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	548 // DSP debug trace type config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	549 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	550 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	551 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	552
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	553 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	554 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	555 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	556 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	557 /* d_error_status */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	558 /-------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	559
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	560 #if ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	561 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	562
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	563 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	564 #define DSP_DEBUG_GSM_MASK 0x0000
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	565 #define DSP_DEBUG_GPRS_MASK 0x0f3d
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	566 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	567
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	568 #if DCO_ALGO
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	569 // DCO type of scheduling
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	570 #define C_CN_DCO_PARAM 0xA248
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	571 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	572
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	573 #elif (DSP == 34) // ROM Code GPRS AMR.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	574 #define CLKMOD1 0x4006 // ...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	575 #define CLKMOD2 0x4116 // ...65 Mips pll free
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	576 #define CLKSTART 0x29 // ...65 Mips
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	577 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	578 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	579 #define AEC 1 // AEC/NS not supported.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	580 #if (OP_RIV_AUDIO == 0)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	581 #define L1_NEW_AEC 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	582 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	583 // Available but not yet tuned with Riviera AUDIO
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	584 #define L1_NEW_AEC 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	585 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	586 #if ((L1_NEW_AEC) && (!AEC))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	587 // First undef the flag to avoid warnings at compilation time
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	588 #undef AEC
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	589 #define AEC 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	590 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	591 #define MAP 3
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	592
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	593 #define DSP_START 0x7000
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	594
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	595 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	596
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	597 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	598 #define ULYSSE 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	599
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	600 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	601
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	602 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	603
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	604 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	605
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	606 // management.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	607
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	608 // DSP_IDLE3 is not supported in simulation
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	609
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	610 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	611 #define W_A_DSP_IDLE3 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	612 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	613
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	614 // DSP software work-around config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	615 // bit0 - Work-around to support CRTG.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	616 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	617 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	618 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	619 #if (ANALOG == 1) // OMEGA / NAUSICA
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	620 #define C_DSP_SW_WORK_AROUND 0x0006
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	621
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	622 #elif (ANALOG == 2) // IOTA
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	623 #define C_DSP_SW_WORK_AROUND 0x000E
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	624
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	625 #elif (ANALOG == 3) // SYREN
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	626 #define C_DSP_SW_WORK_AROUND 0x000E
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	627
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	628 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	629
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	630 /* DSP debug trace configuration */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	631 /-------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	632 #if (MELODY_E2)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	633 // In case of the melody E2 the DSP trace must be disable because the
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	634 // melody instrument waves are overlayed with DSP trace buffer
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	635
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	636 // DSP debug trace API buufer config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	637 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	638 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	639
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	640 // DSP debug trace type config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	641 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	642 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	643 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	644
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	645 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	646 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	647 // Currently not supported !
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	648 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	649 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	650 // DSP debug trace API buufer config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	651 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	652 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	653
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	654 // DSP debug trace type config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	655 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	656 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	657 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	658
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	659 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	660 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	661 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	662
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	663 // AMR trace
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	664 #define C_AMR_TRACE_ID 55
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	665
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	666 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	667 /* d_error_status */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	668 /-------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	669
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	670 #if ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	671 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	672
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	673 // masks to apply on d_error_status bit field
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	674 #define DSP_DEBUG_GSM_MASK 0x0000
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	675 #define DSP_DEBUG_GPRS_MASK 0x0f3d
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	676 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	677
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	678 #elif (DSP == 35) // ROM Code GPRS AMR.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	679 #define CLKMOD1 0x4006 // ...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	680 #define CLKMOD2 0x4116 // ...65 Mips pll free
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	681 #define CLKSTART 0x29 // ...65 Mips
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	682 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	683 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	684 #define AEC 1 // AEC/NS not supported.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	685 #if (OP_RIV_AUDIO == 0)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	686 #define L1_NEW_AEC 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	687 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	688 // Available but not yet tuned with Riviera AUDIO
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	689 #define L1_NEW_AEC 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	690 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	691 #if ((L1_NEW_AEC) && (!AEC))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	692 // First undef the flag to avoid warnings at compilation time
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	693 #undef AEC
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	694 #define AEC 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	695 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	696 #define MAP 3
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	697
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	698 #define FF_L1_TCH_VOCODER_CONTROL 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	699 #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	700
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	701 #define DSP_START 0x7000
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	702
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	703 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	704
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	705 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	706 #define ULYSSE 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	707
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	708 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	709
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	710 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	711
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	712 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	713
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	714 // management.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	715
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	716 // DSP_IDLE3 is not supported in simulation
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	717
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	718 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	719 #define W_A_DSP_IDLE3 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	720 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	721
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	722 // DSP software work-around config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	723 // bit0 - Work-around to support CRTG.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	724 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	725 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	726 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	727 #if (ANALOG == 1) // OMEGA / NAUSICA
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	728 #define C_DSP_SW_WORK_AROUND 0x0006
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	729
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	730 #elif (ANALOG == 2) // IOTA
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	731 #define C_DSP_SW_WORK_AROUND 0x000E
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	732
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	733 #elif (ANALOG == 3) // SYREN
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	734 #define C_DSP_SW_WORK_AROUND 0x000E
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	735
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	736 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	737
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	738 /* DSP debug trace configuration */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	739 /-------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	740 #if (MELODY_E2)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	741 // In case of the melody E2 the DSP trace must be disable because the
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	742 // melody instrument waves are overlayed with DSP trace buffer
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	743
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	744 // DSP debug trace API buufer config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	745 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	746 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	747
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	748 // DSP debug trace type config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	749 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	750 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	751 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	752
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	753 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	754 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	755 // Currently not supported !
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	756 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	757 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	758 // DSP debug trace API buufer config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	759 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	760 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	761
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	762 // DSP debug trace type config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	763 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	764 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	765 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Timer + Buffer Header + Burst.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	766
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	767 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	768 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	769 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	770
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	771 // AMR trace
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	772 #define C_AMR_TRACE_ID 55
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	773
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	774 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	775 /* d_error_status */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	776 /-------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	777
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	778 #if ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	779 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	780
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	781 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	782 #define DSP_DEBUG_GSM_MASK 0x08BD
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	783 #define DSP_DEBUG_GPRS_MASK 0x0f3d
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	784 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	785 #elif (DSP == 36) // ROM Code GPRS AMR.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	786 #define CLKMOD1 0x4006 // ...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	787 #define CLKMOD2 0x4116 // ...65 Mips pll free
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	788 #define CLKSTART 0x29 // ...65 Mips
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	789 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	790 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	791 #define AEC 1 // AEC/NS not supported.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	792 #if (OP_RIV_AUDIO == 0)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	793 #define L1_NEW_AEC 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	794 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	795 // Available but not yet tuned with Riviera AUDIO
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	796 #define L1_NEW_AEC 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	797 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	798 #if ((L1_NEW_AEC) && (!AEC))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	799 // First undef the flag to avoid warnings at compilation time
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	800 #undef AEC
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	801 #define AEC 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	802 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	803 #define MAP 3
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	804 #undef L1_AMR_NSYNC
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	805 #define L1_AMR_NSYNC 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	806 #define FF_L1_TCH_VOCODER_CONTROL 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	807 #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	808
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	809 #define DSP_START 0x7000
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	810
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	811 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	812
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	813 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	814 #define ULYSSE 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	815
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	816 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	817
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	818 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	819
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	820 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	821
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	822 // management.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	823
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	824 // DSP_IDLE3 is not supported in simulation
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	825
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	826 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	827 #define W_A_DSP_IDLE3 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	828 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	829
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	830 // DSP software work-around config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	831 // bit0 - Work-around to support CRTG.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	832 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	833 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	834 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	835 #if (ANALOG == 1) // OMEGA / NAUSICA
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	836 #define C_DSP_SW_WORK_AROUND 0x0006
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	837
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	838 #elif (ANALOG == 2) // IOTA
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	839 #define C_DSP_SW_WORK_AROUND 0x000E
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	840
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	841 #elif (ANALOG == 3) // SYREN
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	842 #define C_DSP_SW_WORK_AROUND 0x000E
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	843 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	844
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	845 // This workaround should be enabled only for H2-sample on full build config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	846 #if (OP_L1_STANDALONE==1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	847 #define RAZ_VULSWITCH_REGAUDIO 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	848 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	849
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	850 /* DSP debug trace configuration */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	851 /-------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	852 #if (MELODY_E2)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	853 // In case of the melody E2 the DSP trace must be disable because the
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	854 // melody instrument waves are overlayed with DSP trace buffer
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	855
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	856 // DSP debug trace API buufer config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	857 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	858 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	859
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	860 // DSP debug trace type config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	861 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	862 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	863 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	864
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	865 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	866 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	867 // Currently not supported !
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	868 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	869 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	870 // DSP debug trace API buufer config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	871 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	872 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	873
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	874 // DSP debug trace type config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	875 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	876 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	877 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	878
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	879 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	880 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	881 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	882
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	883 // AMR trace
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	884 #define C_AMR_TRACE_ID 55
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	885
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	886 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	887 /* d_error_status */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	888 /-------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	889
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	890 #if ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	891 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	892
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	893 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	894 #define DSP_DEBUG_GSM_MASK 0x08BD
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	895 #define DSP_DEBUG_GPRS_MASK 0x0f3d
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	896 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	897 #endif // DSP
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	898
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	899 /------------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	900 /* Default value */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	901 /------------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	902 #ifndef W_A_DSP1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	903 #define W_A_DSP1 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	904 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	905
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	906 #ifndef DATA14_4
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	907 #define DATA14_4 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	908 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	909
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	910 #ifndef W_A_ITFORCE
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	911 #define W_A_ITFORCE 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	912 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	913
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	914 #ifndef W_A_DSP_IDLE3
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	915 #define W_A_DSP_IDLE3 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	916 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	917
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	918 #ifndef L1_NEW_AEC
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	919 #define L1_NEW_AEC 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	920 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	921
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	922 #ifndef DSP_DEBUG_TRACE_ENABLE
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	923 #define DSP_DEBUG_TRACE_ENABLE 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	924 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	925
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	926 #ifndef DEBUG_DEDIC_TCH_BLOCK_STAT
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	927 #define DEBUG_DEDIC_TCH_BLOCK_STAT 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	928 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	929
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	930 #ifndef D_ERROR_STATUS_TRACE_ENABLE
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	931 #define D_ERROR_STATUS_TRACE_ENABLE 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	932 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	933
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	934 #ifndef L1_GTT
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	935 #define L1_GTT 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	936 #define TTY_SYNC_MCU 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	937 #define TTY_SYNC_MCU_2 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	938 #define L1_GTT_FIFO_TEST_ATOMIC 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	939 #define NEW_WKA_PATCH 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	940 #define OPTIMISED 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	941 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	942
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	943 #ifndef L1_AMR_NSYNC
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	944 #define L1_AMR_NSYNC 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	945 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	946
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	947 #ifndef FF_L1_TCH_VOCODER_CONTROL
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	948 #define FF_L1_TCH_VOCODER_CONTROL 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	949 #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	950 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	951
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	952 /------------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	953 /* Download */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	954 /------------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	955
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	956
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	957 /* Possible values for the download status */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	958
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	959 #define LEAD_READY 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	960 #define BLOCK_READY 2
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	961 #define PROGRAM_DONE 3
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	962 #define PAGE_SELECTION 4
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	963
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	964
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	965 /************************************/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	966 /* Options of compilation... */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	967 /************************************/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	968
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	969 // Possible choice of hardware plateform.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	970 #define GEMINI 1 // GEMINI chip (rom dsp code)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	971 #define POLESTAR 2 // POLESTAR chip (no rom)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	972
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	973 // Possible choice for DSP software setup.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	974 #define NO_DWNLD 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	975 #define PATCH_DWNLD 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	976 #define DSP_DWNLD 2
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	977 #define PATCH_DSP_DWNLD 3
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	978
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	979 // MAC-S status reporting to Layer 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	980 #define MACS_STATUS 0 // MAC-S STATUS activated if set to 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	981
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	982
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	983 // Possible choice for dll_dcch_downlink interface (with FN or without FN)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	984 #define SEND_FN_TO_L2_IN_DCCH 1 /* 0=without, 1=with FN parameter */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	985
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	986 //---------------------------------------------------------------------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	987
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	988 // Neighbor Cell RXLEV indication
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	989 #if ((OP_L1_STANDALONE==1) && (CODE_VERSION == NOT_SIMULATION))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	990 #define L1_MPHC_RXLEV_IND_REPORT_SORT 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	991 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	992 #define L1_MPHC_RXLEV_IND_REPORT_SORT 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	993 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	994
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	995 #endif /* __L1_CONFG_H__ */

FreeCalypso > hg > freecalypso-sw

annotate gsm-fw/L1/include/leo-based/l1_confg.h @ 992:a7b0b426f9ca