FreeCalypso > hg > freecalypso-sw
annotate gsm-fw/L1/dyn_dwl_include/l1_dyn_dwl_signa.h @ 992:a7b0b426f9ca
target-utils: boot ROM UART autodetection revamped
The new implementation should work with both the familiar Calypso C035
boot ROM version found in our regular targets as well as the older
Calypso F741979B version found on the vintage D-Sample board.
author | Mychaela Falconia <falcon@ivan.Harhan.ORG> |
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date | Wed, 30 Dec 2015 21:28:41 +0000 |
parents | 3c850b416c9a |
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rev | line source |
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3c850b416c9a
integrating more L1 header files needed by the abb+spi code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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1 /************* Revision Controle System Header ************* |
3c850b416c9a
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2 * GSM Layer 1 software |
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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3 * L1_DYN_DWL_SIGNA.H |
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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4 * |
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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5 * Filename l1_dyn_dwl_signa.h |
3c850b416c9a
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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6 * Copyright 2004 (C) Texas Instruments |
3c850b416c9a
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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7 * |
3c850b416c9a
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
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8 ************* Revision Controle System Header *************/ |
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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9 #if (L1_DYN_DSP_DWNLD == 1) |
3c850b416c9a
integrating more L1 header files needed by the abb+spi code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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10 |
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11 #ifndef _L1_DYN_DWL_SIGNA_H_ |
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12 #define _L1_DYN_DWL_SIGNA_H_ |
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13 |
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14 #define P_DYN_DWNLD 0x41 |
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integrating more L1 header files needed by the abb+spi code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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15 |
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16 // Messages L1S -> L1A |
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17 #define L1_DYN_DWNLD_STOP_CON ( ( P_DYN_DWNLD << 8 ) | 0x02 ) |
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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18 |
3c850b416c9a
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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19 // Messages API HISR -> L1A // |
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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20 #define API_L1_DYN_DWNLD_START_CON ( ( P_DYN_DWNLD << 8 ) | 0x03 ) |
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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21 #define API_L1_DYN_DWNLD_FINISHED ( ( P_DYN_DWNLD << 8 ) | 0x04 ) |
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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22 #define API_L1_DYN_DWNLD_STOP ( ( P_DYN_DWNLD << 8 ) | 0x05 ) |
3c850b416c9a
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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23 #define API_L1_CRC_NOT_OK ( ( P_DYN_DWNLD << 8 ) | 0x07 ) |
3c850b416c9a
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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24 #define API_L1_CRC_OK ( ( P_DYN_DWNLD << 8 ) | 0x08 ) |
3c850b416c9a
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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25 #define API_L1_DYN_DWNLD_UNINST_OK ( ( P_DYN_DWNLD << 8 ) | 0x09 ) |
3c850b416c9a
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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26 |
3c850b416c9a
integrating more L1 header files needed by the abb+spi code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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27 #endif //_L1_DYN_DWL_SIGNA_H_ |
3c850b416c9a
integrating more L1 header files needed by the abb+spi code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
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28 |
3c850b416c9a
integrating more L1 header files needed by the abb+spi code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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29 #endif // L1_DYN_DSP_DWNLD |
3c850b416c9a
integrating more L1 header files needed by the abb+spi code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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