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annotate gsm-fw/bsp/flashchipinit.S @ 923:10b4bed10192

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gsm-fw/L1: fix for the DSP patch corruption bug The L1 code we got from the LoCosto fw contains a feature for DSP CPU load measurement. This feature is a LoCosto-ism, i.e., not applicable to earlier DBB chips (Calypso) with their respective earlier DSP ROMs. Most of the code dealing with that feature is conditionalized as #if (DSP >= 38), but one spot was missed, and the MCU code was writing into an API word dealing with this feature. In TCS211 this DSP API word happens to be used by the DSP code patch, hence that write was corrupting the patched DSP code.
author Mychaela Falconia <falcon@ivan.Harhan.ORG>
date Mon, 19 Oct 2015 17:13:56 +0000
parents 2768b4339275
children
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2768b4339275 a flash chip init/reset function added to Application_Initialize(),
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1 /*
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2 * TI's TCS211 firmware is designed to autodetect the flash chip type for
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3 * its FFS, selecting different FFS configurations depending on what flash
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4 * chip is found. In our FreeCalypso fw we fix our FFS configuration at
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5 * compile time instead (for us it's more a matter of either mimicking or
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6 * working around what the previous firmwares on our target devices do),
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7 * so we have no "proper" place for flash chip type autodetection logic in
2768b4339275 a flash chip init/reset function added to Application_Initialize(),
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8 * our fw architecture.
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9 *
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10 * However, the following function (to be executed out of IRAM) mimics the
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11 * sequence of flash chip accesses performed by TCS211's flash chip type
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12 * autodetection function. It was added in a stray hope that it might fix
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13 * the perplexing crash behavior we see when booting on a GTA02 modem that
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14 * is "hot", i.e., powered off and then back on without giving it a long
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15 * time to "cool".
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16 */
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17
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18 .code 32
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19 .text
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20
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21 .globl flash_chip_init
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22 flash_chip_init:
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23 ldr r1, =0x0300AAAA
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24 ldr r2, =0x03005555
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25 ldr r3, =0x03000000
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26 /* read ID mode sequence */
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27 mov r0, #0xAA
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28 strh r0, [r1]
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29 mov r0, #0x55
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30 strh r0, [r2]
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31 mov r0, #0x90
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32 strh r0, [r1]
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33 /* dummy reads */
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34 ldrh r0, [r3, #0]
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35 ldrh r0, [r3, #2]
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36 /* Intel reset command */
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37 mov r0, #0xFF
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38 strh r0, [r3]
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39 /* AMD reset sequence */
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40 mov r0, #0xAA
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41 strh r0, [r1]
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42 mov r0, #0x55
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43 strh r0, [r2]
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44 mov r0, #0xF0
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45 strh r0, [r1]
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46 bx lr