FreeCalypso > hg > freecalypso-schem2
log
| age | author | description | 
|---|---|---|
| Fri, 19 Nov 2021 18:57:57 +0000 | Mychaela Falconia | Venus MCL: add 74LVC125A for Calypso UART inputs | 
| Fri, 19 Nov 2021 06:48:25 +0000 | Mychaela Falconia | venus/src/periph/battery.v: adapted from FCDEV3B | 
| Fri, 19 Nov 2021 06:44:53 +0000 | Mychaela Falconia | venus/src/periph/sma_wrap.v: unchanged from FCDEV3B | 
| Fri, 19 Nov 2021 06:09:13 +0000 | Mychaela Falconia | Venus core: bring out SIM_CD | 
| Fri, 19 Nov 2021 05:58:21 +0000 | Mychaela Falconia | Venus: first version of Verilog for the Calypso core | 
| Fri, 19 Nov 2021 03:47:49 +0000 | Mychaela Falconia | Venus primitives: add TRRS jack | 

