# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1637970348 0
# Node ID d33cb696b335dc565c088411ed1d38a9a2068380
# Parent  df16d0eabf8a32a23e35799f00682d85ef2a22b8
add missing bypass caps for mobile domain peripherals

diff -r df16d0eabf8a -r d33cb696b335 venus/src/MCL
--- a/venus/src/MCL	Fri Nov 26 23:32:00 2021 +0000
+++ b/venus/src/MCL	Fri Nov 26 23:45:48 2021 +0000
@@ -234,6 +234,18 @@
  footprint=0402
  npins=2
 
+# Bypass cap for U401
+C402:
+ hier=mob.uart.U401_bypass
+ footprint=0402
+ npins=2
+
+# Bypass cap for U402
+C403:
+ hier=mob.sim.inv_bypass
+ footprint=0402
+ npins=2
+
 C600:
  hier=mob.core.rf.rita2pa_hb.C600
  footprint=0402
diff -r df16d0eabf8a -r d33cb696b335 venus/src/periph/calypso_uart_in.v
--- a/venus/src/periph/calypso_uart_in.v	Fri Nov 26 23:32:00 2021 +0000
+++ b/venus/src/periph/calypso_uart_in.v	Fri Nov 26 23:45:48 2021 +0000
@@ -14,6 +14,9 @@
 /* U401 buffer common part */
 logic_ic_common U401_common (.Vcc(Vio), .GND(GND));
 
+/* bypass capacitor */
+capacitor U401_bypass (Vio, GND);
+
 /* buffer slots */
 buffer_slot_3state Host_TxD_buffer  (.A(Host_TxD),  .nOE(GND), .Y(RX_MODEM));
 buffer_slot_3state Host_RTS_buffer  (.A(Host_RTS),  .nOE(GND), .Y(CTS_MODEM));
diff -r df16d0eabf8a -r d33cb696b335 venus/src/periph/sim_socket_block.v
--- a/venus/src/periph/sim_socket_block.v	Fri Nov 26 23:32:00 2021 +0000
+++ b/venus/src/periph/sim_socket_block.v	Fri Nov 26 23:45:48 2021 +0000
@@ -35,4 +35,7 @@
 			  .Y(SIM_CD)
 		);
 
+/* bypass cap for the inverting buffer IC */
+capacitor inv_bypass (Vio, GND);
+
 endmodule