# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1639117219 0
# Node ID adc84e0e98d6c168d5318b3a0bce0a26a0638f9d
# Parent  93b238ad7d6e3df5d6ac18265f3a4f575b7eb1d2
add 74AXP1T34 buffer for flash reset

diff -r 93b238ad7d6e -r adc84e0e98d6 venus/src/MCL
--- a/venus/src/MCL	Fri Dec 10 05:58:58 2021 +0000
+++ b/venus/src/MCL	Fri Dec 10 06:20:19 2021 +0000
@@ -1611,6 +1611,16 @@
  grid_pkg=TPA6203A1-bga.pkg
  pinout=TPA6203A1-bga.pinmap
 
+U303:
+ hier=mob.core.bb.dbb.ON_nOFF_2V8_buffer.pkg
+ device=74AXP1T34
+ manufacturer=Nexperia
+ manufacturer_part_number=74AXP1T34GMH
+ description=Logic voltage level translating buffer, SOT886 package
+ vendor=Digi-Key
+ vendor_part_number=1727-2482-1-ND
+ npins=6
+
 U401:
  device=74LVC125A
  manufacturer=Nexperia
diff -r 93b238ad7d6e -r adc84e0e98d6 venus/src/core/baseband.v
--- a/venus/src/core/baseband.v	Fri Dec 10 05:58:58 2021 +0000
+++ b/venus/src/core/baseband.v	Fri Dec 10 06:20:19 2021 +0000
@@ -5,7 +5,7 @@
  */
 
 module baseband (GND, VBAT, VSIM, Vio, Vflash, Vsram,
-		 PWON, RPWON, nTESTRESET, ON_nOFF, CLKTCXO_IN,
+		 PWON, RPWON, nTESTRESET, ON_nOFF, ON_nOFF_2V8, CLKTCXO_IN,
 		 TDI, TDO, TCK, TMS,
 		 MCU_A, MCU_D, MCU_RnW, MCU_nFWE, MCU_nFOE, MCU_FDP,
 		 MCU_nBLE, MCU_nBHE, MCU_nCS,
@@ -29,7 +29,7 @@
 output VSIM, Vio, Vflash, Vsram;
 
 input PWON, RPWON, nTESTRESET;
-output ON_nOFF;
+output ON_nOFF, ON_nOFF_2V8;
 
 input CLKTCXO_IN;
 
@@ -187,7 +187,8 @@
 		.SIM_IO(DBBSIO),
 		.SIM_CLK(DBBSCLK),
 		.SIM_RST(DBBSRST),
-		.SIM_CD(SIM_CD)
+		.SIM_CD(SIM_CD),
+		.ON_nOFF_2V8(ON_nOFF_2V8)
 	);
 
 abb_block abb ( .GND(GND),
diff -r 93b238ad7d6e -r adc84e0e98d6 venus/src/core/core.v
--- a/venus/src/core/core.v	Fri Dec 10 05:58:58 2021 +0000
+++ b/venus/src/core/core.v	Fri Dec 10 06:20:19 2021 +0000
@@ -86,6 +86,7 @@
 wire Vflash, Vsram;
 wire MCU_FDP, MCU_nBLE, MCU_nBHE;
 wire INT_nCS0, INT_nCS1, INT_nCS2;
+wire ON_nOFF_2V8;
 
 /* instantiate the blocks! */
 
@@ -99,6 +100,7 @@
 	     .RPWON(RPWON),
 	     .nTESTRESET(nTESTRESET),
 	     .ON_nOFF(ON_nOFF),
+	     .ON_nOFF_2V8(ON_nOFF_2V8),
 	     .CLKTCXO_IN(Clock_26MHz_DBB_in),
 	     .TDI(TDI),
 	     .TDO(TDO),
@@ -200,7 +202,7 @@
 	    .MCU_nWR(MCU_RnW),
 	    .MCU_nBHE(MCU_nBHE),
 	    .MCU_nBLE(MCU_nBLE),
-	    .Flash_RST(MCU_FDP),
+	    .Flash_RST(ON_nOFF_2V8),
 	    .CS_flash1(INT_nCS0),
 	    .CS_RAM(INT_nCS1)
 	);
diff -r 93b238ad7d6e -r adc84e0e98d6 venus/src/core/dbb_block.v
--- a/venus/src/core/dbb_block.v	Fri Dec 10 05:58:58 2021 +0000
+++ b/venus/src/core/dbb_block.v	Fri Dec 10 06:20:19 2021 +0000
@@ -7,6 +7,9 @@
  * - nBSCAN and nEMU[1:0] no-connects.
  *
  * All other Calypso signals are passed through untouched.
+ *
+ * The buffer that produces a 2.8V version of the ON_nOFF signal for
+ * flash reset is also included here.
  */
 
 module dbb_block (GND, Vdbb, Vio, Vflash, Vrtc,
@@ -24,7 +27,7 @@
 		  BFSR, BDR, BFSX, BDX, BCLKX_IO6, BCLKR_ARMCLK,
 		  VDX, VDR, VFSRX, VCLKRX,
 		  MCUDI, MCUDO, MCUEN0, MCUEN1_IO8, MCUEN2_IO13,
-		  SIM_IO, SIM_CLK, SIM_RST, SIM_CD);
+		  SIM_IO, SIM_CLK, SIM_RST, SIM_CD, ON_nOFF_2V8);
 
 input GND, Vdbb, Vio, Vflash, Vrtc;
 
@@ -80,6 +83,8 @@
 output SIM_CLK, SIM_RST;
 input SIM_CD;
 
+output ON_nOFF_2V8;
+
 /* nets inside this module */
 wire SIM_PWCTRL;
 wire GND_32khz, OSC32K_IN, OSC32K_OUT, OSC32K_OUT_2;
@@ -209,4 +214,13 @@
 /* SIM_PWCTRL resistor like on Leonardo schematics */
 resistor R207 (SIM_PWCTRL, SIM_IO);
 
+/* ON_nOFF_2V8 buffer */
+
+buffer_74AXP1T34 ON_nOFF_2V8_buffer (.GND(GND),
+				     .Vcci(VDD_CORE),
+				     .Vcco(Vflash),
+				     .A(ON_OFF),
+				     .Y(ON_nOFF_2V8)
+	);
+
 endmodule