# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1639118619 0
# Node ID 96e02b1b23743480cb7517836a8012276c2e8f8a
# Parent  adc84e0e98d6c168d5318b3a0bce0a26a0638f9d
change flash+RAM MCP to S71PL129N

diff -r adc84e0e98d6 -r 96e02b1b2374 venus/src/MCL
--- a/venus/src/MCL	Fri Dec 10 06:20:19 2021 +0000
+++ b/venus/src/MCL	Fri Dec 10 06:43:39 2021 +0000
@@ -1596,9 +1596,9 @@
 U301:
  hier=mob.core.mem.chip.pkg
  manufacturer=Spansion
- manufacturer_part_number=S71PL064JA0BFW0B
+ manufacturer_part_number=S71PL129NC0HFW4B
  description=Memory IC, combined flash and pSRAM
- grid_pkg=pkg_TLC056.bgadef
+ grid_pkg=pkg_TLA064.bgadef
 
 U302:
  hier=mob.spkr.apa
diff -r adc84e0e98d6 -r 96e02b1b2374 venus/src/core/core.v
--- a/venus/src/core/core.v	Fri Dec 10 06:20:19 2021 +0000
+++ b/venus/src/core/core.v	Fri Dec 10 06:43:39 2021 +0000
@@ -204,6 +204,7 @@
 	    .MCU_nBLE(MCU_nBLE),
 	    .Flash_RST(ON_nOFF_2V8),
 	    .CS_flash1(INT_nCS0),
+	    .CS_flash2(INT_nCS2),
 	    .CS_RAM(INT_nCS1)
 	);
 
diff -r adc84e0e98d6 -r 96e02b1b2374 venus/src/core/memory.v
--- a/venus/src/core/memory.v	Fri Dec 10 06:20:19 2021 +0000
+++ b/venus/src/core/memory.v	Fri Dec 10 06:43:39 2021 +0000
@@ -1,15 +1,15 @@
 module memory  (GND, Vflash, Vsram,
 		MCU_A, MCU_D, MCU_nRD, MCU_nWR, MCU_nBHE, MCU_nBLE,
-		Flash_RST, CS_flash1, CS_RAM);
+		Flash_RST, CS_flash1, CS_flash2, CS_RAM);
 
 input GND, Vflash, Vsram;
 input [22:1] MCU_A;
 inout [15:0] MCU_D;
 input MCU_nRD, MCU_nWR, MCU_nBHE, MCU_nBLE;
 input Flash_RST;
-input CS_flash1, CS_RAM;
+input CS_flash1, CS_flash2, CS_RAM;
 
-S71PL064J chip (.Flash_Vcc(Vflash),
+S71PL129N chip (.Flash_Vcc(Vflash),
 		.RAM_Vcc(Vsram),
 		.Vss(GND),
 		.A(MCU_A),
@@ -17,6 +17,7 @@
 		.OE(MCU_nRD),
 		.WE(MCU_nWR),
 		.Flash_CE1(CS_flash1),
+		.Flash_CE2(CS_flash2),
 		.Flash_RST(Flash_RST),
 		.Flash_WP_ACC(Vflash),
 		.Flash_ready_busy(),	/* no connect */