# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1638408934 0
# Node ID 8f3df7a222f544771ea8a82937be99a5dd2ad61e
# Parent  473c0c52eaed0f1732aebd40c8fb2bf9c677d06d
change USB 6.0 MHz crystal to a smaller part

diff -r 473c0c52eaed -r 8f3df7a222f5 venus/src/MCL
--- a/venus/src/MCL	Thu Dec 02 00:36:28 2021 +0000
+++ b/venus/src/MCL	Thu Dec 02 01:35:34 2021 +0000
@@ -1618,11 +1618,10 @@
  npins=4
 
 X701:
- hier=usb.usb.FT2232D.xtal
- manufacturer=IQD
- manufacturer_part_number=LFXTAL026900
- description=Crystal, 6.0 MHz, 16 pF, HC-49 SMT
+ hier=usb.usb.FT2232D.xtal.xtal
+ manufacturer=Raltron
+ manufacturer_part_number=H13-6.000-16-5050-EXT-TR
+ description=Crystal, 6.0 MHz, 16 pF, 7x5 mm SMT
  vendor=Digi-Key
- vendor_part_number=1923-1509-1-ND
- footprint=HC49_SMT
- npins=2
+ vendor_part_number=2151-H13-6.000-16-5050-EXT-TRCT-ND
+ npins=4
diff -r 473c0c52eaed -r 8f3df7a222f5 venus/src/Makefile
--- a/venus/src/Makefile	Thu Dec 02 00:36:28 2021 +0000
+++ b/venus/src/Makefile	Thu Dec 02 01:35:34 2021 +0000
@@ -22,7 +22,7 @@
 	usb/FT2232D_block.v usb/FT2232D_chip.v usb/eeprom_93Cx6_16bit.v \
 	usb/regulator_ic.v usb/regulator_with_caps.v usb/usb_conn.v \
 	usb/usb_core.v usb/usb_domain.v usb/usb_domain_bctl.v \
-	usb/usb_domain_buf.v
+	usb/usb_domain_buf.v usb/usb_xtal_wrap.v
 SLOTMAP=slotmap/Q308 slotmap/Q402 slotmap/Q600 slotmap/Q601 \
 	slotmap/R295 slotmap/R296 slotmap/R361 \
 	slotmap/U401 slotmap/U403 slotmap/U705 slotmap/U707
diff -r 473c0c52eaed -r 8f3df7a222f5 venus/src/usb/FT2232D_block.v
--- a/venus/src/usb/FT2232D_block.v	Thu Dec 02 00:36:28 2021 +0000
+++ b/venus/src/usb/FT2232D_block.v	Thu Dec 02 01:35:34 2021 +0000
@@ -68,7 +68,7 @@
 
 /* crystal oscillator */
 
-xtal_2pin_pkg xtal (XTIN, XTOUT);
+usb_xtal_wrap xtal (XTIN, XTOUT, GND);
 capacitor XTIN_cap (XTIN, GND);
 capacitor XTOUT_cap (XTOUT, GND);
 
diff -r 473c0c52eaed -r 8f3df7a222f5 venus/src/usb/usb_xtal_wrap.v
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/usb/usb_xtal_wrap.v	Thu Dec 02 01:35:34 2021 +0000
@@ -0,0 +1,16 @@
+/*
+ * This Verilog module encapsulates the PCB footprint
+ * for our 6.0 MHz USB crystal.
+ */
+
+module usb_xtal_wrap (electrode1, electrode2, GND);
+
+input electrode1, electrode2, GND;
+
+xtal_4pin_pkg xtal (.pin_1(electrode1),
+		    .pin_2(GND),
+		    .pin_3(electrode2),
+		    .pin_4(GND)
+	);
+
+endmodule