# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1637355554 0
# Node ID 5b18183f55bfb51cdae3af942217e5b1b6e7d3ef
# Parent  3d5c40988a6b3cc731e03a05b3ecd2cfdde0a9e1
Venus src: SIM socket block captured

diff -r 3d5c40988a6b -r 5b18183f55bf venus/src/periph/sim_socket_block.v
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/periph/sim_socket_block.v	Fri Nov 19 20:59:14 2021 +0000
@@ -0,0 +1,38 @@
+/*
+ * This module encapsulates the complete SIM socket block:
+ * the actual socket, the bypass cap and our SIM_CD circuit.
+ */
+
+module sim_socket_block (GND, Vio, VSIM, SIM_CLK, SIM_RST, SIM_IO, SIM_CD);
+
+input GND, Vio, VSIM;
+input SIM_CLK, SIM_RST;
+inout SIM_IO;
+output SIM_CD;
+
+wire SIM_CD_inverted;
+
+sim_socket_wrap socket (.C1(VSIM),
+			.C2(SIM_RST),
+			.C3(SIM_CLK),
+			.C5(GND),
+			.C6(VSIM),
+			.C7(SIM_IO),
+			.SW1(GND),
+			.SW2(SIM_CD_inverted)
+		);
+
+/* cap per Leonardo schematics */
+capacitor C306 (VSIM, GND);
+
+/* pull-up on the switch line */
+resistor switch_pullup (SIM_CD_inverted, Vio);
+
+/* inverting buffer for SIM_CD */
+inv_buffer_74LVC1G04 inv (.GND(GND),
+			  .Vcc(Vio),
+			  .A(SIM_CD_inverted),
+			  .Y(SIM_CD)
+		);
+
+endmodule
diff -r 3d5c40988a6b -r 5b18183f55bf venus/src/periph/sim_socket_wrap.v
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/periph/sim_socket_wrap.v	Fri Nov 19 20:59:14 2021 +0000
@@ -0,0 +1,18 @@
+/* This module is a wrapper around our SIM socket with card detect switch */
+
+module sim_socket_wrap (C1, C2, C3, C5, C6, C7, SW1, SW2);
+
+inout C1, C2, C3, C5, C6, C7;
+inout SW1, SW2;
+
+pkg_SIM_socket socket (	.pin_1(C1),
+			.pin_2(C2),
+			.pin_3(C3),
+			.pin_4(SW1),
+			.pin_5(C5),
+			.pin_6(C6),
+			.pin_7(C7),
+			.pin_8(SW2)
+		);
+
+endmodule