# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1638325359 0
# Node ID 3afd172b83e13c77686f22c84f5fc9d149846a5b
# Parent  ec932276c8e636fbfc1f2705b34629c46ab44fb9
main audio channel implemented

diff -r ec932276c8e6 -r 3afd172b83e1 venus/src/MCL
--- a/venus/src/MCL	Sat Nov 27 20:43:23 2021 +0000
+++ b/venus/src/MCL	Wed Dec 01 02:22:39 2021 +0000
@@ -256,6 +256,57 @@
  footprint=0402
  npins=2
 
+C410:
+ hier=mob.audio_main.C32
+ footprint=0402
+ npins=2
+
+C411:
+ hier=mob.audio_main.C21
+ footprint=0402
+ npins=2
+
+C412:
+ hier=mob.audio_main.C12
+ footprint=0402
+ npins=2
+
+C413:
+ hier=mob.audio_main.C13
+ value=10uF
+ footprint=0805
+ npins=2
+
+C414:
+ hier=mob.audio_main.C14
+ footprint=0402
+ npins=2
+
+C415:
+ hier=mob.audio_main.C15
+ footprint=0402
+ npins=2
+
+C416:
+ hier=mob.audio_main.C16
+ footprint=0402
+ npins=2
+
+C417:
+ hier=mob.audio_main.C17
+ footprint=0402
+ npins=2
+
+C418:
+ hier=mob.audio_main.C18
+ footprint=0402
+ npins=2
+
+C419:
+ hier=mob.audio_main.C19
+ footprint=0402
+ npins=2
+
 C600:
  hier=mob.core.rf.rita2pa_hb.C600
  footprint=0402
@@ -632,6 +683,7 @@
 
 # Main audio jack
 J401:
+ hier=mob.audio_main.jack.pkg
  manufacturer=CUI
  manufacturer_part_number=SJ1-42514-SMT-TR
  description=2.5 mm audio jack, TRRS, no switch, SMT
@@ -683,6 +735,18 @@
 
 # Inductors
 
+L401:
+ hier=mob.audio_main.L1
+ value=100n
+ footprint=0402
+ npins=2
+
+L402:
+ hier=mob.audio_main.L2
+ value=100n
+ footprint=0402
+ npins=2
+
 L600:
  hier=mob.core.rf.rita2pa_hb.L600
  footprint=0402
@@ -1036,6 +1100,12 @@
  footprint=0402
  npins=2
 
+R415:
+ hier=mob.audio_main.R9
+ value=2.2k
+ footprint=0402
+ npins=2
+
 # attenuators in the Tx path from Rita to PA
 part chip_atten:
  device=RAC101A-3dB
diff -r ec932276c8e6 -r 3afd172b83e1 venus/src/Makefile
--- a/venus/src/Makefile	Sat Nov 27 20:43:23 2021 +0000
+++ b/venus/src/Makefile	Wed Dec 01 02:22:39 2021 +0000
@@ -8,13 +8,14 @@
 	core/rfmatch_rita2pa_hb.v core/rfmatch_rita2pa_lb.v \
 	core/rita_rf_chip.v core/rita_vcxo_int.v core/rita_wrap.v \
 	core/xtal_32khz_wrap.v \
-	periph/MAX1916.v periph/Si9407AEY.v periph/battery.v \
-	periph/bl_current_select.v periph/bl_current_sink.v \
+	periph/MAX1916.v periph/Si9407AEY.v periph/audio_main.v \
+	periph/battery.v periph/bl_current_select.v periph/bl_current_sink.v \
 	periph/calypso_uart_in.v periph/charging_circuit.v \
 	periph/charging_led.v periph/inv_buffer_74LVC1G04.v periph/jtag_if.v \
 	periph/keypad.v periph/keyswitch_wrap.v periph/lcd_module.v \
 	periph/lcd_subsystem.v periph/led_mosfet.v periph/led_npn.v \
 	periph/sim_socket_block.v periph/sim_socket_wrap.v periph/sma_wrap.v \
+	periph/trrs_jack.v \
 	top/board.v top/mobile.v \
 	usb/FT2232D_block.v usb/FT2232D_chip.v usb/eeprom_93Cx6_16bit.v \
 	usb/regulator_ic.v usb/regulator_with_caps.v usb/usb_conn.v \
diff -r ec932276c8e6 -r 3afd172b83e1 venus/src/periph/audio_main.v
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/periph/audio_main.v	Wed Dec 01 02:22:39 2021 +0000
@@ -0,0 +1,51 @@
+/*
+ * This Verilog module encapsulates our main audio channel.
+ */
+
+module audio_main (GND, EARN, EARP, MICBIAS, MICIN, MICIP);
+
+input GND;
+input EARN, EARP;
+input MICBIAS;
+output MICIN, MICIP;
+
+/* internal wires */
+
+wire EARN_jack, EARP_jack, MIC_jack;
+
+/* instantiate the jack */
+
+trrs_jack jack (.T(EARP_jack),
+		.R(MIC_jack),
+		.R2(EARN_jack),
+		.S(GND),
+		.T_sw(),	/* not used */
+		.R_sw()		/* not used */
+	);
+
+/* earpiece path filter caps */
+
+capacitor C15 (EARP, EARN);
+capacitor C16 (EARP, GND);
+capacitor C17 (EARP, GND);
+capacitor C18 (EARN, GND);
+capacitor C19 (EARN, GND);
+
+/* earpiece path filter inductors */
+
+inductor L1 (EARP, EARP_jack);
+inductor L2 (EARN, EARN_jack);
+
+/* microphone input circuit */
+
+capacitor C13 (MICBIAS, GND);
+
+resistor R9 (MICBIAS, MIC_jack);
+capacitor C14 (MIC_jack, GND);
+
+capacitor C12 (MICBIAS,  MICIP);
+capacitor C21 (MIC_jack, MICIN);
+
+capacitor C32 (MICIP, MICIN);
+
+endmodule
diff -r ec932276c8e6 -r 3afd172b83e1 venus/src/periph/trrs_jack.v
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/periph/trrs_jack.v	Wed Dec 01 02:22:39 2021 +0000
@@ -0,0 +1,19 @@
+/*
+ * This Verilog module encapsulates the physical PCB footprint pinout
+ * of the TRRS jack part we are using.
+ */
+
+module trrs_jack (T, R, R2, S, T_sw, R_sw);
+
+inout T, R, R2, S;
+inout T_sw, R_sw;
+
+pkg_TRRS_jack pkg (.pin_1(S),
+		   .pin_2(T),
+		   .pin_3(R),
+		   .pin_4(R2),
+		   .pin_5(T_sw),
+		   .pin_6(R_sw)
+	);
+
+endmodule
diff -r ec932276c8e6 -r 3afd172b83e1 venus/src/top/mobile.v
--- a/venus/src/top/mobile.v	Sat Nov 27 20:43:23 2021 +0000
+++ b/venus/src/top/mobile.v	Wed Dec 01 02:22:39 2021 +0000
@@ -205,6 +205,16 @@
 led_npn    led_LPG  (.GND(GND), .VBAT(VBAT), .Signal(DSR_LPG));
 led_npn    led_PWL  (.GND(GND), .VBAT(VBAT), .Signal(LT_PWL));
 
+/* audio circuits */
+
+audio_main audio_main ( .GND(GND),
+			.EARN(EARN),
+			.EARP(EARP),
+			.MICBIAS(MICBIAS),
+			.MICIN(MICIN),
+			.MICIP(MICIP)
+	);
+
 /* SIM socket */
 sim_socket_block sim (.GND(GND),
 		      .Vio(Vio),