# HG changeset patch # User Mychaela Falconia # Date 1639167965 0 # Node ID 09cda55086b15a4b9a45e6387ac38bf331067e75 # Parent 96e02b1b23743480cb7517836a8012276c2e8f8a venus/doc/Flash+RAM written diff -r 96e02b1b2374 -r 09cda55086b1 venus/doc/Flash+RAM --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/venus/doc/Flash+RAM Fri Dec 10 20:26:05 2021 +0000 @@ -0,0 +1,84 @@ +All historical Calypso phone or modem designs which we (FreeCalypso) consider +interesting enough to copy use a combined MCP (multi-chip package) for their +flash and XRAM, the latter being our term for board-level RAM, as opposed to the +relatively small IRAM inside the Calypso chip itself. The following Spansion +MCPs (all of them no longer made and available only from surplus, sadly) are +most interesting to us: + +* S71PL032J (4 MiB flash, various RAM options) would be fine for an AT-command- + controlled modem like Openmoko - however, we are not building any such product + at the present, and this flash capacity is too small for the functionality + that must be supported on FC Venus. + +* S71PL064J is 8 MiB flash with various RAM options; S71PL064JA0 is the version + with 2 MiB RAM. The latter part is used inside mass-produced iWOW TR-800 + modules - there is a rumor that they may have used S71PL064JB0 initially, + with 4 MiB RAM, but then went down to 2 MiB - but S71PL064JA0 is the chip + inside those TR-800 modules which are presently available as a large surplus. + This chip seems ideal: 8 MiB flash + 2 MiB XRAM is sufficient memory capacity + for all TCS211 firmware configurations, and the physical footprint of 7x9 mm + is the smallest we've ever seen for such MCPs. + +* S71PL129J and S71PL129N are 16 MiB flash families, presented as two flash chip + select banks of 8 MiB each, specifically made for use with processors like + Calypso that have a limit of 8 MiB per chip select. RAM options are + correspondingly large; the chip used on FCDEV3B (copied from Pirelli DP-L10) + is S71PL129NC0HFW4B, and the XRAM capacity is 8 MiB. Compared to S71PL-J + chips, S71PL129N has more stringent reset timing requirements; the impact on + Calypso-based designs is that Calypso FDP output cannot be used as the flash + reset signal, and a different circuit based on ON_nOFF signal is needed - and + the latter circuit requires adding one more little IC, Nexperia 74AXP1T34, a + dual supply translating buffer. The latter design with 74AXP1T34 has been + proven on FCDEV3B V2. + +As far as FC Venus PCB design goes, meaning flash+RAM MCP footprint and the +flash reset circuit, the following options are up for consideration: + +Option 1: copy the 7x9 mm MCP footprint from iWOW TR-800. This footprint +accommodates S71PL064J but not S71PL129J or N; because populating S71PL129N is +not possible on this footprint, flash reset can be sourced from Calypso FDP +output as was done in TI's original design. + +Option 2: enlarge the MCP footprint to 8x11.6 mm with 8 extra mechanical-only +balls, but keep the old and simple reset circuit. This option will allow +populating either S71PL064J or S71PL129J, but not S71PL129N - the latter would +cause sleep mode problems and sometimes even boot problems as seen on FCDEV3B V1 +where we made this mistake. + +Option 3: use the larger MCP footprint for 16 MiB flash and also incorporate the +74AXP1T34 flash reset circuit from FCDEV3B V2. This option will allow any of +S71PL064J, S71PL129J or S71PL129N to be populated and work correctly. + +The Mother's original plan for FC Venus was to do Option 1, but this plan is now +being changed to Option 3. The reasons for this change are: + +* S71PL129NC0HFW4B parts are already on hand at FreeCalypso HQ, and have been + used successfully in FCDEV3B board builds. With Option 1 we would need to go + back to our Chinese grey market supplier and procure S71PL064J chips, and then + take the risk of possibly bad parts. + +* For psychological reasons it is important for FC Venus to be a no-worse + successor to FCDEV3B. Even though 8 MiB flash + 2 MiB XRAM is perfectly + sufficient memory capacity for all of our fw configurations (and according to + TI's docs, it would be sufficient even for their pdt_2272 config with MMS + functionality, which we don't have), a reduction from FCDEV3B's 16 MiB flash + + 8 MiB XRAM will undoubtedly be seen by some community members as a downgrade. + There is also potential value in being able to load and run non-flashed + fc-xram firmware builds, which is only possible with gigantic 8 MiB XRAM. + +* Because *all* of our suitable Spansion MCP options are no-longer-made + surplus-only parts (much like the core Calypso chipset itself), it makes good + sense to design our PCB in such a way as to allow as many options as possible, + not excluding any otherwise suitable (and known) option through our PCB + design choices. + +The downside of this chosen approach (compared to our original approach of +Option 1) is the increase in MCP BGA footprint, plus the little bit of extra +room needed for the 74AXP1T34 IC. The Leonardo core layout inside TR-800 is +very tight with no room for any extras, thus if we were seeking to clone or +semi-clone a Tango module, this increase in PCB real estate for the flash+RAM +MCP would not be acceptable. However, in the case of FC Venus, our core +shieldcan section already includes many additions beyond Leonardo/TR-800: +consider U401 through U404, all of which need to go into this expanded core +section. Thus if we are already expanding the core for other reasons, we should +be able to throw in this flash+RAM MCP expansion as well.