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view venus/src/periph/Si9407AEY.v @ 36:c1256c8757c3

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eliminate R209 and tie Iota VLMEM directly to UPR We already eliminated R210 (VLMEM pull-down option) earlier, because our simplified LCD power supply and reset line wiring is incompatible with 1.8V MEMIF. But with VLMEM always needing to be high, a pull-up resistor offers no advantage over a direct tie to UPR, so let's eliminate the superfluous resistor.
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 22 Nov 2021 19:19:59 +0000
parents 74a89c0a6466
children
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/*
 * This Verilog module encapsulates a MOSFET in a Si9407AEY-compatible
 * SOIC-8 footprint.
 */

module Si9407AEY (G, S, D);

input G, S;
output D;

/* instantiate the package; the mapping of signals to pins is defined here */

pkg_IC_8pin pkg (.pin_1(S),
		 .pin_2(S),
		 .pin_3(S),
		 .pin_4(G),
		 .pin_5(D),
		 .pin_6(D),
		 .pin_7(D),
		 .pin_8(D)
	);

endmodule