view venus/src/core/rita_vcxo_int.v @ 9:3ed0f7a9c489

Venus: first version of Verilog for the Calypso core
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 19 Nov 2021 05:58:21 +0000
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/*
 * This module encapsulates the Rita block (Rita chip + caps) together with
 * the choice of internal or external VC(TC)XO; this version is for the
 * internal configuration.
 */

module rita_vcxo_int (GND, VBAT, VREG3, VRIO,
		      TCXOEN, RFEN, AFC_in, Clock_out_to_DBB,
		      Ctrl_CLK, Ctrl_DATA, Ctrl_STROBE, Ctrl_RESETZ,
		      IN, IP, QN, QP,
		      LNAGSMN, LNAGSMP, LNADCSN, LNADCSP, LNAPCSN, LNAPCSP,
		      LBTXOUT, HBTXOUT,
		      DAC, DET1, DET2, APC,
		      RTEMP_VTEST);

input GND, VBAT, VRIO;
output VREG3;

input TCXOEN, RFEN, AFC_in;
output Clock_out_to_DBB;

input Ctrl_CLK, Ctrl_DATA, Ctrl_STROBE, Ctrl_RESETZ;
inout IN, IP, QN, QP;

input LNAGSMN, LNAGSMP, LNADCSN, LNADCSP, LNAPCSN, LNAPCSP;
output LBTXOUT, HBTXOUT;

input DAC, DET1, DET2;
output APC;

output RTEMP_VTEST;

/* internal VCTCXO configuration */

wire XIN;

int_vcxo_passive vcxo_passive (AFC_in, XIN, GND);

/*
 * Some Leonardo schematic versions show a "resistor short" with refdes R604
 * between TCXOEN from the Calypso and the net going to XEN, XSEL and the cap
 * or two caps.  In Openmoko's version this component is a physical 0402 SMT
 * 0R jumper; in iWOW TR-800 this series R has been measured to be 47 Ohm
 * instead.  On FC Venus we shall include an 0402 series R footprint
 * just in case.
 */

wire TCXOEN_after_0R;

resistor R604 (TCXOEN, TCXOEN_after_0R);

/* instantiate the Rita block */

rita_wrap rita (.GND(GND),
		.VBAT(VBAT),
		.VREG3(VREG3),
		.VRIO(VRIO),
		.XEN(TCXOEN_after_0R),
		.XSEL(TCXOEN_after_0R),
		.XIN(XIN),
		.Clock_out_to_DBB(Clock_out_to_DBB),
		.Ctrl_CLK(Ctrl_CLK),
		.Ctrl_DATA(Ctrl_DATA),
		.Ctrl_STROBE(Ctrl_STROBE),
		.Ctrl_RESETZ(Ctrl_RESETZ),
		.IN(IN),
		.IP(IP),
		.QN(QN),
		.QP(QP),
		.LNAGSMN(LNAGSMN),
		.LNAGSMP(LNAGSMP),
		.LNADCSN(LNADCSN),
		.LNADCSP(LNADCSP),
		.LNAPCSN(LNAPCSN),
		.LNAPCSP(LNAPCSP),
		.LBTXOUT(LBTXOUT),
		.HBTXOUT(HBTXOUT),
		.DAC(DAC),
		.DET1(DET1),
		.DET2(DET2),
		.APC(APC),
		.RTEMP_VTEST(RTEMP_VTEST)
	);

endmodule