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Venus: first version of Verilog for the Calypso core
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 19 Nov 2021 05:58:21 +0000
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/* RF Tx path from Rita to PA, low bands */

module rfmatch_rita2pa_lb (In, Out, GND);

input In;
output Out;
input GND;

wire mid1, mid2;

inductor L601 (In, mid1);
capacitor C655 (mid1, mid2);
chip_attenuator R600 (mid2, Out, GND, GND);

endmodule