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view venus/src/periph/inv_buffer_74LVC1G04.v @ 18:2f344ca2c1e4

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Venus src: jtag_if.v adapted from FCDEV3B
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 20 Nov 2021 04:32:50 +0000
parents 3d5c40988a6b
children
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module inv_buffer_74LVC1G04 (GND, Vcc, A, Y);

input GND, Vcc;
input A;
output Y;

/* instantiate the package; the mapping of signals to pins is defined here */

pkg_XSON6 pkg  (.pin_1(),	/* no connect */
		.pin_2(A),
		.pin_3(GND),
		.pin_4(Y),
		.pin_5(),	/* no connect */
		.pin_6(Vcc)
	);

endmodule